dai
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- dai
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Hi @Matthias, I tried with specify certain name and the result is same. With "all cells" I did not get the message more. I sent you the test case by email, please check your email. Thank you, dai
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Thank you, @Matthias dai
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i saw it in forum. :) thank @StefanThiede dai
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Thank you, @StefanThiede can you show more detail?. Where do i find this tool on klayout? (Image) dai
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Hi @Matthias , like above we can do on GUI. can we do compare layout vs layout like above by macro?. Please let me know If you have any code example. Thank you, dai
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Hi @Matthes , It works perfectly Thank you, dai
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Thank you, @sekigawa dai
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Hi @Max, Thank you for asking. I have done my macro so it is fine for me now. But if i have ChipR i want to compare speed with it to see if i can improve my macro more. dai
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hi @Matthias it is working now. Thank you very much,@Matthias. :) dai
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Hi @Matthias Yes, it is an invalid layer id. Thank you, dai
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Hi @Matthias , I found the cause for it. There are some layers merged to one. (Image) Thank you, dai
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Hi @dick_freebird , I'm not sure i understand all your thing. the technology i doing with just support two type of via( square(32x32), rectangle(32x80)) In this case i just want to flag to @Matthias about the error. I trying extract resistor of spe…
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Thank you, @dick_freebird and @Matthias I think i have to subdivide net into pieces because my net is complex and layout guys just want to show resistance between two specified points that they can select. dai
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Thank you, @Matthias My connector should be on short edge of via if shape of via is rectangle(this relate to value of resistor). If it just square then don't need to care it is horizontal or vertical. connector = via.extents(0,1.dbu) it works also…
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Hi @Matthias BTW Have any function help to calculate resistance from node 5 to node 6 in this picture?. I can not use netlist.simplify Because it combine all resistor to one. I trying to flag where is high resistor compare others. (Image) Thank y…
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Hello @Matthias Yes, it is terminals. i trying extract resistor of polygon shape(L,T.. shape), i split polygons to squares and each square is a resistor so it form resistor like that. Here is a example. (Image) Thank you so much. dai
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Thank you, @Matthias
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Hi @hycmos Thank you very much. Can you give us the link to download ChipR again? I can not download from the link you sent. dai
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Thank you, @Matthias dai
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Thank you, @Matthias dai
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Thank you, @Matthias I have extended the edge to tiny polygon(i know it is not good solution but it can resolve my issue) and apply space DRC to them (Quote) Here is the way i created the edges, (Quote) i also attached the layout here. thanks dai
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Thank @Matthias. Thank @dick_freebird.
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Hi @Matthias Do you have any way to ignore or set tolerance for parameter for SVS check?. two my netlists has a different width of device so it flag connection mismatch also. It should be show property mismatch only. Thank you, dai
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Hi Matthias Thank you for answering me. Yes, i mean no GUI mode. You are right. I found my issue now, because i have two .lyt files with same technology name( in subfolders in the tech folder), when Klayout turn on(with -b option) one of them was o…
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yes, run time is ok for me now, it is so good with non-commercial tool. i run script on with GUI it work ok but when i change to run on command mode(no GUI) this mean i can not use trace(string tech,const Layout layout,const Cell cell,const Point st…
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thanks you, @Matthias it work for me dai
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hi Matthias yes, i'm sorry i can not send you the gds but this is not important. BTW, do you have any way to find where is the shorted net when we have a shorted net(ex: vdd vs vss)?. when i click on the net it show on whole layout so it is hard to …
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hi @Matthias I tried run with smaller cell(1.2MB) it took around 30s to pass the command(top_cir = netlist.circuit_by_name(curCell)). I see it take time for "computing local cluster" and "computing hierarchical cluster" (Image) …
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hi @Matthias , The issue with pin as i showed above (Image) after i remove the un-expected pin to avoid app crash(at "compare" function) i have to find these nets on top of the sub(removed pin)to delete also: net.subcircuit_pin_count == …
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Hi @Matthias First time i used name of pins for equivalent_pins function, i think i made something wrong so it not work, after that i changed to used index of pin(equivalent_pins (cirname,1,2....)), it work. now i can run lvs for Standard cell, IO …