Here is a macro :
https://www.klayout.de/forum/discussion/368/dice-count-gross-die-yield-and-wafermap-on-a-layout
This is the same method as my Android app : Wafer gross die yield and cost
But with KLayout, you get the wafermap in GDS format as a r…
Assuming a via width of 100nm, I solved it this way :
via.enclosed(metal, projection, 20.nm, two_opposite_sides_allowed, one_side_allowed).with_length(100.nm).output("Metal enclosing via > 20nm on two opposite sides")
BRgds,
Laurent
Assuming a via width of 100nm, I solved it this way :
via.enclosed(metal, projection, 20.nm, two_opposite_sides_allowed, one_side_allowed).with_length(100.nm).output("Metal enclosing via > 20nm on two opposite sides")
BRgds,
Laurent
Oups, my exact command was :
via.enclosed(metal, projection, 20.nm, two_opposite_sides_allowed, three_sides_allowed).output("Metal enclosing via > 20nm on two opposite sides")
BRgds,
Laurent
I just found out that the following command does not work in some strange cases below :
via.enclosed(metal, projection, 20.nm, two_sides_allowed, three_sides_allowed).output("Metal enclosing via > 20nm on two opposite sides")
(Image)
…
Synopsys has its explanation here : https://www.synopsys.com/glossary/what-is-parasitic-extraction.html
StarRC is based on Look-Up tables : it could be a target for KLayout - but which look-up tables ?
QuickCapNX is a 3D field solver for RF
Actually, there are 2 kinds of parasitic extraction : a precise one for RF, any LNA or antenna needs a precises R and C extraction, maybe in 3-D. But for the digital place&route a less precise extraction but fast R-C extraction will do it. The s…
"original" for me is the result of place&route of OpenROAD. I am trying to run some check on it, so "original" can be rectangles, polygons or paths from the current level of a hierarchy below.
BRgds,
Laurent
Indeed, I was using the deep mode, but with random shapes (polygons, paths, ...). Now, it works fine in tile mode, but not in deep mode :'(
As usual, I was using your latest version ;) , now, I use the version of December 2.
Laurent
Thank you Matthias, furthermore I needed to mixed moved and sized functions, it perfectly meets my need, except ... that I cannot resize the result. As in your exemple :
sized_bottom_left = original.sized(0.5.um, 0).sized(0, 0.5.um).moved(0.5.um, -…
Actually, OpenRCX does not extract the parasitic ; it calls the software recommended by the foundry (a commercial tool :s ) as it is explained here :
https://github.com/The-OpenROAD-Project/OpenRCX/blob/master/doc/calibration.txt
Laurent
Thank you Matthias, it more efficient than my command. As I like to have the all DRC check in 1 line I have compacted as follows : ;)
M1.edges.without_angle(0).without_angle(90).without_angle(45).without_angle(-45).output("M1_angle", &qu…
By the way, if the klayout lvsdb file that results from a KLayout LVS could be read by XSCHEM to find the correspondence between schematic and layout, it would be great :smiley:
Laurent
Thank you Matthias, yep, it seems to be for the same process ... and it works fine ... my next step is to add the body pin.
@dick : the third pins is used to add the parasitic capacitance, and my case, yes, it the bulk :p ! and the LVS is OK :)
B…
I just find that the proper syntax is :
extract_devices(resistor_with_bulk("RPolyRes_Bulk", 333), { "R" =>; resistor, "C" =>; poly_not_resistor, "W" >; bulk })
This OK to check a resistor like : R0…
Thank you Matthias and Stefan. I found my way to write the file for the OpenROAD flow as I wrote in :
https://github.com/The-OpenROAD-Project/OpenROAD/discussions/1919
BRgds,
Laurent
Hi Jim,
Here a complete xml file compatible with in-line execution :
<?xml version="1.0" encoding="utf-8"?><klayout-macro> <description/> <version/> <category>drc</category> <prolog/> &…
Hi Matthias,
Thank you, then the method for the second case becomes :
VM1 = VIA.enclosed(METAL, 0.01, projection, one_side_allowed)VM2 = VIA.enclosed(METAL, 0.01, projection, two_sides_allowed)VM3 = VIA.enclosed(METAL, 0.01, projection, three_side…
Is there a way to use the waivers options like for the separation check ?
For example, for 2 opposite sides :
METAL.enclosing(VIA, 0.01, projection, one_side_allowed, two_sides_allowed).output("METAL_enc_VIA", "rule xy : Min. Metal …
Hi Michael,
Did you succeeded to make a proper C extraction from a GDS ? or someone else ?
If yes, can you share some example files (GDS, qui and spice file) ?
It seems that xictools is the software to use ...
Laurent
Hi Michael,
Did you succeeded to make a proper C extraction from a GDS ? or someone else ?
If yes, can you share some example files (GDS, qui and spice file) ?
It seems that xictools is the software to use ...
Laurent
I confirmed that I have sometimes to follow some design rules with a defined radius ... that is double checked by my subcontractor ... this arc ruler definitly has some application !
Laurent