lvs
false
false
true
lvs_scripts
tools_menu.lvs.end
dsl
lvs-dsl-xml
schematic("empty_subcells.cir")
deep
report_lvs("lvs.log")
target_netlist("rcx.cir", write_spice(true, false), "Generated by Klayout")
m1 = input(1, 0)
via = input(2, 0)
m2 = input(3, 0)
lab = labels(254,0)
connect(m1, via)
connect(via, m2)
connect(m2, lab)
netlist.make_top_level_pins
#netlist.blank_circuit("block*")
#netlist.flatten
#align
#netlist.simplify
#consider_net_names(true)
compare