1.0
lvs
true
false
true
lvs_scripts
tools_menu.lvs.end
dsl
lvs-dsl-xml
#!/usr/bin/ruby
deep
#######################################################################################
# Reports generated:
report_lvs("lvs.lvsdb") # LVS report window
path_gds = RBA::CellView::active.filename
#topCell = File.basename(path_gds, ".*")
curCell = RBA::CellView::active.cell_name
ly = RBA::CellView::active.layout
#define layer in layout
nwell = input(3, 0)
active = input(6, 0)
od_srm = input(6, 11)
cmd = input(84, 20)
pplus = input(25, 0)
nplus = input(26, 0)
poly = input(17, 0)
cpo = input(17, 11) + input(17, 12)
m0_od = input(84, 0)
m0_po = input(84, 2)
gated = input(255,3)
# Computed layers:
poly_outside_cpo = poly - cpo
poly_outside_cpo_podegate = poly_outside_cpo
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly_outside_cpo_podegate
psd = pactive - pgate
ntie = active & nwell & nplus
ptie = (active - nwell) & pplus
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly_outside_cpo_podegate
nsd = nactive - ngate
m0_od_outside_cmd = m0_od - cmd
bulk = polygon_layer
puts "extractions [" + Time.now.strftime("%M:%S") + "]"
#IO
# PMOS transistor device extraction
extract_devices(mos4("PCH_SVT_MAC"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly_outside_cpo, "tW" =>
nwell })
# NMOS transistor device extraction
extract_devices(mos4("NCH_SVT_MAC"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly_outside_cpo, "tW" =>
bulk })
connect(psd, m0_od_outside_cmd)
connect(nsd, m0_od_outside_cmd)
connect(ntie, m0_od_outside_cmd)
connect(ptie, m0_od_outside_cmd)
connect(poly_outside_cpo, m0_po)
connect(m0_od_outside_cmd, m0_po)
connect(nwell,ntie)
# Global
#netlist.flatten_circuit("SUBL3")
puts netlist.to_s