# A simple CMOS process description demonstrating:
# - Well formation
# - Field oxide formation
# - Gate formation with LDD spacers/implant 
# - W plug creating and W CMP
# - First metal layer formation

# Basic options: declare the depth of the simulation and the height.
# These are the defaults 2.0 / 2.0:
depth(10.0)
height(38.0)
# Declare the basic accuracy used to remove artefacts for example:
delta(10 * dbu)

# Declaration the layout layers.
# Possible operations are (l1 = layer(..); l2 = layer(..))
#   "or"     l1.or(l2)
#   "and"    l1.and(l2)
#   "xor"    l1.xor(l2)
#   "not"    l1.not(l2)
#   "size"   l1.sized(s)     (s in micron units)
#     or     l1.sized(x, y)  (x, y in micron units)
#   "invert" l1.inverted

lpoly = layer("7/0")
lactive = layer("4/0")
lfox = lactive.inverted
lnw = layer("1/0")
lnpiu = layer("2/0")
lppiu = layer("3/0")
lcon = layer("10/0")
lm1 = layer("11/0")
lhtr = layer("51/0")
lta = layer("50/0")
lvias = layer("20/0")
lm2 = layer("21/0")
lpass = layer("52/0")
lff = layer ("113/0")
ldrie = layer ("109/0")
lpinp = layer ("114/0")



# Process steps:
# Now we move to cross section view: from the layout geometry we create 
# a material stack by simulating the process step by step. 
# The basic idea is that all activity happens at the surface. We can
# deposit material (over existing or at a mask), etch material and
# planarize. 
# A material is a 2D geometry as seen in the cross section along the
# measurement line.
# The following steps mimic a simple process.

# Start with the p doped bulk and assign that to material "pbulk"
# "bulk" delivers the wafer's cross section. 
pbulk = bulk

# create a n-well by growing the mask into the pbulk material. The
# pbulk material is consumed by this step.
nwell = mask(lnw).grow(2, 1, :mode => :round, :bias => 0.5, :into => pbulk)

# field oxide formation: we use the mask twice, once to grow upwards and 
# once to grow into the existing material. We use round approximation to 
# build a "hill", although that is not showing the typical beak. 
# Note, that we first derive the mask and use it twice. That ensures we 
# use the same seed for both contributions. Afterwards we join the 
# contributions to form the field oxide.
# "bias" will shrink the resulting area.
active = mask(lactive)
mfox = mask(lfox)
fox1 = mfox.grow(0.5, 0.2, :bias => 0.1, :mode => :round)
fox2 = mfox.grow(0.5, 0.2, :bias => 0.1, :mode => :round, :into => [pbulk, nwell])
fox = fox1.or(fox2)

# deposit 20nm gate oxide.
# "deposit" is an alias for "all.grow" where "all" is a special mask covering "everything".
gox = deposit(0.02)

# Vt boron implant blanket - need artificial masks to be present only under poly on not in n-well
mvt = lpoly.and(lnw.inverted)
vt = mask(mvt).grow(0.02, :into => [pbulk], :through => gox)

# create poly --> could be improve conformity on top of FOX if deposit and then mask/etch
poly = mask(lpoly).grow(0.45, -0.05, :mode => :round)

# implant the LDD areas. Note the "through" specification which allows to grow into the 
# pbulk/nwell even if covered by GOX (normally that would prevent).
# Also note, that "diffuse" is actually an alias for "all.grow".
# mnldd is artificial mask, to prevent to show nldd in p+ regions
mnldd = lppiu.inverted
nldd = mask(mnldd).grow(0.08, 0.2, :into => [pbulk, nwell], :through => gox, :mode => :round)

# implant the p+ and n+ source drain regions
pp = mask(lppiu).grow(0.2, 0.1, :into => [nldd, nwell, pbulk], :through => [gox, nldd], :mode => :round)
np = mask(lnpiu).grow(0.2, 0.1, :into => [nwell, pbulk, pp], :through => [gox, nldd], :mode => :round)

# remove gate oxide where not covered 
etch(0.02, :into => gox)

# deposit isolation
iso = deposit(0.7, 0.5, :mode => :round)

# etch the gate and source/drain contacts
# "taper" will make the holes conical with a sidewall angle of 5 degree.
mask(lcon).etch(1, :into => iso, :taper => 5)
mask(lcon).etch(0.6, :into => fox, :taper => 5)

# m1 metal deposition mask and etch 
htr = deposit(0.075, 0.075)
alu1 = deposit(0.45, 0.45)
mask(lm1.inverted).etch(1, :into => [alu1, htr], :taper => 8)
mask(lm1.inverted).etch(0.1, :into => fox, :taper => 8)

# mask etch sloped metal etch
mask(lhtr).etch(0.7, :bias => -1.25, :into => alu1, :taper => 70)

# deposit SiN
sinit = deposit(0.2, 0.2, :mode => :round)
# deposit Ta
tant = deposit(0.35, 0.35, :mode => :round)

# mask-etch sinit and tant
mask(lta.inverted).etch(1.5, :into => [sinit, tant], :taper => 4)
mask(lta.inverted).etch(0.1, :into => fox, :taper => 0)

# deposit IMD and reb
imd = deposit(2.5, 1, :mode => :round)
planarize(:into => [imd], :less => 0.95)

# mask etch Vias on IMD, alu, Ta and FOX
mask(lvias).etch(3, :into => imd, :taper => 7)
mask(lvias).etch(0.05, :into => alu1, :taper => 0)
mask(lvias).etch(0.07, :into => tant, :taper => 0)
mask(lvias).etch(0.1, :into => fox, :taper => 7)

# deposit etch metal2
alu2 = deposit(1.1, 1.1)
mask(lm2.inverted).etch(4, :bias => -0.7, :into => alu2, :taper => 15)

# dep passivation
po = deposit(0.8, 0.2)
mask(lpass).etch(1.3, :into => po, :taper => 0)
mask(lpass).etch(0.73, :into => iso, :taper => 0)
mask(lpass).etch(0.03, :into => tant, :taper => 0)
mask(lpass).etch(0.5, :into => fox, :taper => 0)

# MEMS FLOW Start

#Flow Feature coat + dummylayer for planarization coat + nozzle coat and FF exp/develop
flowfeat = deposit(20, 20)
dum1 = deposit(20, 20)
planarize(:downto => flowfeat, :into => dum1)
planarize(:less => 7, :into => [ dum1, flowfeat ])
nozzle = deposit(14, 14)
mask(lff).etch(34, :into => flowfeat, :through => nozzle)

# PINP coat/exp/develop

mask(lpinp).etch(15, :into => nozzle, :taper => 0)

# process from the backside - artifact to make negative tapering profile
flip

#DRIE silicon etch
mask(ldrie).etch(12, :into => pbulk, :taper => 7)

# swap back frontside 
flip

# finally output all result material.
# output specification can be scattered throughout the script but it is 
# easier to read when put at the end.
output("300/0 - P-Substrate", pbulk)
output("301/0 - N-Well", nwell)
output("302/0 - Field Oxide", fox)
output("303/0 - Gate Oxide", gox)
output("340/0 - Vt Impl", vt)
output("304/0 - Poly", poly)
output("305/0 - N-Ldd", nldd)
output("306/0 - P+ S/D", pp)
output("307/0 - N+ S/D", np)
output("308/0 - PMD", iso)
output("309/0 - Heater TaAlN", htr)
output("310/0 - MT1 AlCu", alu1)
output("311/0 - SiN", sinit)
output("312/0 - Tantalum", tant)
output("313/0 - IMD", imd)
output("314/0 - MT2 AlCu", alu2)
output("315/0 - Passivation", po)
output("316/0 - Flow Feature", flowfeat)
output("317/0 - PINP", nozzle)
layers_file("CMOS3JP_XSEM.lyp")