We can develop the appropriate compatibility tools for dialect differences, or Mr Matthias open the interface to the netlist reader in klayout and override it. I think Mr Matthias does not always have time to handle so many requests.
You can decide how you want to proceed depending on the frequency or number of your needs. If you need to process such pspice files often, it is better to have a script that can batch process them.
Most of the ones that are publicly availa…
And our export format is different because we use different versions of the output software, but the resulting problem is the same, the output spice needs to be read by KLayout through certain modifications.
There are two errors in your File.
1, Regarding netlist, there is no "+" before the parameter
* source OPAMP.SUBCKT opamp M_M4 VOUT VIN VDD VDD MbreakP L=0.18um W=0.54um M_M3 VOUT VIN GND GND MbreakN L…
I now solve this problem by manual modifications, which mainly include removing the $ symbol before some parameters and adding a virtual resistance value to the resistor.
RR0 vdd! gnd! $[RR1] $W=600n $L=6u M=1
Thanks very much for your advice, it has helped me a lot!
In fact this code is a test case I made to reproduce my problem, so the specific Layer assignments and calculations are virtual, as I am not allowed to publish the rules file of th…
The correct version that can finally be run:
#Bian#24.01.2023schematic("mos")deepreport_lvsnwell = input(3, 0)poly = input(2, 0)diff = input(1, 0)sd = diff-poly$dbu_value=dbuclass MOS4Extractor < RBA::GenericDeviceE…
That's not the point, the main thing I don't understand is why layer_geometry is null, extracting through the default extract_devices is not null, even though I used the same input. Even without setting the define_terminal part, la…
Thanks for your suggestions! You mentioned that the index of tSis 3. I found this in file dbNetlistDeviceExtractorClasses.cc: **
**The index of tS here is 5, should I follow the settings in the source code about this index, or i…
Thanks for your detailed and perfect answer, this problem has been solved perfectly!
And I would like to report to you a bug about the "width_check" function, when the third parameter region is entered as nil, it says that n…
I don't know what's wrong with the input of define_terminal, I checked the type of input and my input "define_terminal(device, RBA::DeviceClassDiode::TERMINAL_A, 0, anode);" matches "(1) Signature: void define_terminal (Device ptr dev…
I don't like the resistance value. Another reason is that the value of sheet_ratio I found in the process file itself is variable and complicated.
I used to think that ignoring of the resistance value is the special setting you answered l…
Thanks for your answer. That is the point I mentioned last time
Because if the size of t…
@laurent_c Thanks! That works very well, I didn’t know method .simplify would work for the schematic too :D
But now I've found a new bug, can't simplify multilevel call macros.
For example, re1 is composed of 6 resistors and re2 is composed of 9 re…
@Matthias Based on this individual instance.
I want to compare a macro composed of many identical resistors connected in series. The netlist reader recognizes it as many individual resistors, but after simplifying, only the simplified resistors are…
The original netlist is in pspice format from cadence, there are "$" before variable or modell name.
So I am also very interested in a another question, which format of netlist can klayout-netlist-reader read? Are there any doku…