WENSHIH
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- WENSHIH
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Thanks for your suggestion and helps! If there is any information I can supply, please tell me. Here is the test file.
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The schematic netlist is correct. All the pins are assigned to the right place and the LVS report that there is no problem. The points which confused me are why does the LVS extract the S and D of layout in opposite and why does the LVS still pass w…
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Here is my schematic and schematic netlist. (Image) Does it mean the LVS of klayout would identify the mos that S and D are opposite in pair? Like below. M5 is from the schematic netlist, $2 is from the layout netlist. (Image) Could you please …
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After I add "combine_device" in my scripts, there is the same consequence as before I add "combine_device", the source of mos2 is still connected to op instead of vdd. Could you explain more about how you call the center stripe D…
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@Matthias Thanks for your help! Since I'm not familiar with extracting netlist from the pspice enough, I think I would take some time to summarize the modification I need. But I will try my best. WENSHIH
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@dick_freebird I've seen that discussion either. Is this the discussion that you have mentioned? https://www.klayout.de/forum/discussion/comment/9014#Comment_9014 I've used the way in this discussion, but I still fail.
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@Matthias HI! This problem has been solved. The critical point was like you said. I can successfully proceed LVS after I renamed the name of the model. Thanks! WENSHIH
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@dick_freebird Unfortunately, I have tried every format in pspice, but I still can't find the form that could get a single line per device, Maybe I omitted something, but I didn't find out. I really hope that the LVS could tolerate dialect differen…
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@Bian Thanks for your help! I have been stuck in this problem few days, after I followed your step, it has been successed. I will try to write a script that can batch process them. Thanks again!
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Here is my file. If it can let you more clearly about my problem, you can open it.
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@Bian I have tried every netlist form in pspice, but I still couldn't have the same kind of form as yours. Here is my schematic and the netlist of my schematic (Image) This is my format setting (Image) Could you show me how you set the format o…
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Thanks for your answer! It's really helpful! There is another problem come out, I used the same net name for the schematic and the layout (Image) but the log file says the net mismatched (Image) Does klayout only read the CIR form only? Here is m…
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@Bian Hi! I use the pspice format from cadence too. So I am interested in the same question as you. Could you please share how you deal with this problem if you have found the solution? Thanks!
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Thanks for your answer! As you said, the path looks different, after I change the path in the script, the problem has solved!
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The full path in the popup error window is not the valid path to the.CIR file, the full valid path is "C:\1090513\DESIGN2.CIR", like the second picture. I use the WIN11 machine and my klayout is 0.27.11, but I don't know the meaning of &q…