barlow
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I finally got some time to dip back into this topic. To get around this issue, my solution included some use of the "cheat" function, but that did not consistently fix the issues I was dealing with. I understand the concerns you ( @Matthia…
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@Matthias, Thanks for your response. I'll be perfectly honest, it has been so long since I designed that layout that I had forgot that the sources overlap. I agree that the closer you get layouts, the more likely you are to get into trouble with hie…
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@laurent_c Yes, I have sources overlapping in the design. The gate is fully formed (e.g. BUF1 passes DRC and LVS by itself). Looking at the "cheat" command now to better understand what's going on there.
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See, that's why I'm a bit confused - as far as I can tell the third number is not memory. Memory usage has remained pretty stable, but below 2GB. I think it must be some loop iteration count or something? I'm aware of the halting problem but I am cu…
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That is an insidious edge case for the wildcards. I tried out the same_nets!("*", "?*") bit. I found out that this works roughly as expected, but fails when the schematic net name has only 1 character. In practice, this might no…
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A brief addendum, I tried seeing if I could iterate through the schematic nets to mark which nets can match "anything" and those that can't. Using the nets_by_name("*") and Net.is_internal? I can iterate through the netlist and d…
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@Matthias So in trying out the same_nets!("*", "*") function, I have run into a new issue - now all nets must have names matching in both the schematic and layout. I suppose that result is not too surprising considering the wild…
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@Matthias I did some playing around with versions to see if it might have been something we did with our build process, and I tested several versions. I think I already tested more than I needed, and I'd probably be better served at this point to di…
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To be clear, the provided design on GitHub is correct as provided. I am changing the labels in the layout to help demonstrate the issue that I'm having, where a bottom-up verification scheme "fails" because the labels aren't treated as a r…
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Thank you for your response! I understand topologically everything is correct, but the problem that I run into is when I'm integrating these cells as subcells in a larger schematic/layout. In those cases, my "A" and "B" pins bei…