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By using following sample data, I confirmed LVS normal operation.
Then, I added dummy poly data at both virtical side of INVX1 cell.
This data insertion is common in advanced processes.
As a result, extra pins are generated and the circuit verification
of ringo circuit cannot be completed.
.SUBCKT INVX1 VDD OUT VSS \$4 nc_1 nc_2 IN SUB
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUB NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
How can I suppress this pin generation?