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For latch-up reasons often rules are given that all source/drain area of transistor have to be below a certain distance from the bulk/well contacts (also called taps). Problem I don't know how to get to the result for being in the same well.
The distance is most of the time much bigger than the minimal well dimension. So the N+ tap in a NWELL should not count as pick-up point for a pactive in a neighboring NWELL even if distance is smaller than the required distance.
I don't immediately see how to do this in klayout.