MOSFET 4 terminal extraction

hi Matthias.
i tried to run lvs on klayout 0.27.5 but i have issue with device extraction. After i run my script i click to device on browser it show me like following picture. i dont know why it marked like this. i also try to run with older version (26.7) it show correctly device.
i am not sure it is a bug or not. I also attach my gds and ckt and my script:

report_lvs("lvs.lvsdb") # LVS report window

path_gds = RBA::CellView::active.filename
topCell = File.basename(path_gds, ".")

ptr =path_gds.split /\//
n = ptr.size
filename =
filename = filename.sub(/.[^.]
$/, "")
path_ckt = RBA::CellView::active.filename.sub(/.[^.]*$/, ".ckt")

#define layer in layout
nwell = input(3, 0)
active = input(6, 0)
cmd = input(4, 2)
pplus = input(25, 0)
nplus = input(26, 0)
poly = input(17, 0)
cpo = input(17, 11)
m0_od = input(0,0)
m0_po = input(1,0)
poly_outside_cpo = poly - cpo
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly_outside_cpo
psd = pactive - pgate

active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly_outside_cpo
nsd = nactive - ngate
m0_od_outside_cmd = m0_od - cmd
bulk = polygon_layer

# PMOS transistor device extraction
extract_devices(mos4("PCH"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly_outside_cpo, "tW" =>
nwell })
# NMOS transistor device extraction
extract_devices(mos4("NCH"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly_outside_cpo, "tW" =>
bulk })
connect(psd, m0_od_outside_cmd)
connect(nsd, m0_od_outside_cmd)
connect(poly_outside_cpo, m0_po)
connect_global(bulk, "vss")
connect_global(nwell, "vdd")
same_device_classes("PCH", "PCH_SVT_MAC")
same_device_classes("NCH", "NCH_SVT_MAC")
check = compare

thank you very much!


  • Thanks a lot for the test case.

    However I do not really understand the intention of the layout. It's just showing a single active region of p type separated by many gates which are not connected anywhere. So essentially, there will be many devices (one where the gate splits active into source and drain).

    0.26.7 and 0.27.5 come to the same conclusion, but the device display is more accurate in 0.27.5. A single device is actually only the source and drain region which is directly attached to a specific gate.

    If you want the individual devices to form a big single one (like the schematic suggests), you need to connect sources and drains and gates. Plus you'll need a n type device too by adding n+ active in the p substrate region below.


  • thank for replying me
    Here is just test case, these gates is not folding of circuit is different, i deleted almost and just keep OD and some other layer relate to show this case. when i select S D G of the device($1) it show drain and source together but G is a different place like following picture. if i delete one gate on the right(X postion:-5.371,1.636,0.552) then tool show the device correct position(picture is below)

    Thank again

  • @dai Thank you for this explanation. This is a real glitch. I have created a ticket for this case:

    Thanks for reporting this issue.


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