Multiple devices in the reference netlist

I was able to get LVS working, but only with single devices. The reference netlist reader does not seem to recognize multiple devices (typically M=2 or more). Since I use multiple devices extensively, this is a potential problem for me to be able to use the Klayout LVS. Am I missing something?


  • Just found out combine_devices in the documentation - that appears to be the workaround - but it requires editing the netlist to use the the total W for MOS or total value for capacitors rather that the M parameter. Would be nice if the netlist reader recognized the M= attribute.

  • Hi,

    I don't see how editing is required. Could you provide an example which demonstrates the issue?

    Internally, KLayout does not use the "m" parameter - it always calculates the total width (of MOS devices) or capacitance (for caps).


  • The M parameter is used in the reference netlist. The problem is that Klayout does not recognize it when reading it. That means I have to edit the schematic netlist for LVS to work.

  • Here is an example (BIAS)
    BIAS.cir shows the edits I had to do to make LVS work, for example:

    • M1 BIASP BIASP VDD! VDD! PMOS L=3u W=40u M=2
      M1a BIASP BIASP VDD! VDD! PMOS L=3u W=40u
      M1b BIASP BIASP VDD! VDD! PMOS L=3u W=40u
      BIAS.spc is the netlist extracted when running lvs.lylvs and,
      BIAS.ext is the netlist extracted when running netlist.lylvs

    Some observations:
    1. while both use 'deep', the lvs netlist is flat and the BIAS.ext netlist is hierarchical,

    Both use netlist.simplify, but neither seem to combine devices (such as M$9 and M$10 in BIAS.SPC)

  • Hello @patrickmawet ,

    thanks a lot for providing this test case. It's much better to discuss things on a real case. And there are some things to explain ...

    First a note which may be to interest: instead of putting a fixed path into the LVS script, you can refer to the path of the currently loaded layout, so the script looks up the .cir file next to the layout:

    # extracts the directory from the path of the layout file loaded
    path = File.dirname(source.path)

    Coming to your topics:

    The key topic is the function of "align". This function will compare the cells (subcircuits) from the extracted netlist against the cells (subcircuits) schematic netlist. It does so by comparing the names. If a cell from the extracted netlist is not found in the schematic netlist, the layout cell is flattened - i.e. all components are moved into the parent cell (circuit). The same happens the other way around.

    This already explains why you don't see a hierarchical LVS netlist: because only the top level cell matches a circuit in the schematic, basically everything will be flattened out and a single-hierarchy netlist results (BTW: also for the schematic netlist, but you don't see that).

    Now, if you look at the extracted netlist without "align", you see some hierarchy:

    The hierarchy reaches down to the MOS devices. And this explains why "combine_devices" does not work: "combine_devices" only works locally on circuits and not across hierarchies. So in the case of the unaligned netlists, the algorithm will see four devices in "nmos$w_15$l_4$m_4$" for example, but these are not connected in parallel on this hierarchy level. Hence no combination.

    The solution is simple: just put "align" before "netlist.simplify".

    This has another side effect however: it will also combine the four resistors which are put in series. I don't see you edited this, so I assume you don't want the resistor devices to be combined.

    You can instruct LVS to not consider these devices when combining them, by manipulating the "device class" of these devices:

    cls = extract_devices(resistor("RNP1", 1000), { "R" => rnp1, "C" => pwire })
    cls.supports_serial_combination = false
    cls.supports_parallel_combination = false

    With these changes I get a match with what I think is the original schematic.

    Kind regards,


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