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I’m doing my best to explain this as clearly as possible. I want to verify the overlap of metal layers over a passivation layer. However, I only have one passivation layer that can connect one metal to other metals.
The Design Rule Check (DRC) should work as follows:
1- Verify that the top metal layer TM, which is the common metal and can connect to all other metals through passivation, is larger (e.g., 2um) than the passivation layer (Layer PL). If this is not the case, an error should be returned. (I know how to write this part.)
2- Verify that the gate metal layer (GM) is 2um larger than PL. If this condition is not met, check the second metal, SDM. If this condition is still not met, check the third metal, BGM. If none of these conditions are met, then an error should be returned.
My problem lies in the output, which should be like this:
However, the error is being applied to all vias that have PL on them! I only want the error to be applied to the specific via with the problem.