Command Line Interface in order to handle "Save Layout Options"

By default KLayout saves some cell context information $$$CONTEXT_INFO$$$,
which can be unselected in the "Save Layout Options".
Also I would like to select "Eliminate zero-length paths" by default.

Is it possible to make this changes using command line interface ?
If that would be the case what would be the command to do so ?

Best regards
Krzysztof

Comments

  • Hi Krzystof,

    I think you refer to the default settings, correct?

    Thing is, users can switch this setting and it will stay that way.

    To force this flag to "true", use this code:

    tech = pya.Technology.technology_by_name("")
    options = tech.save_layout_options
    options.gds2_no_zero_length_paths = True
    tech.save_layout_options = options
    

    Matthias

  • @Matthias thank you for providing a solution for ''zero length paths".
    What about the Cell Context ? Is it possible to uncheck it using the same approach as shown below ?

    tech = pya.Technology.technology_by_name("")
    options = tech.save_layout_options
    options.gds2_no_zero_length_paths = True
    options.write_context_info = False
    tech.save_layout_options = options
    
  • Yes, exactly. All options can be configured this way.

    But beware: if you make this the default, users will lose their PCell information when they save their work! This is not user friendly.

    I think you're trying to establish some standards for distributing layouts to the foundry. The usual way to solve that issue is not to force users into a specific mode, but to introduce a layout delivery step into your flow. That is a translation of some GDS file of generic nature into one with known properties. Technically in your case that may mean to load and save a layout while you use the above settings for saving. The result of that operation is sent to the foundry.

    That is also the opportunity to run sanity checks or final DRC for example. Sanity checks can involve checking the presence of certain layers (e.g. chip boundary), compliance with naming conventions, presence of a single top cell etc.

    Matthias

Sign In or Register to comment.