Spice Arguments

Taniwha

I'm new here so first: thanks for KLayout!

I've been using a work flow that's essentially:

• edit something in klayout
• run LVS
• run a spice testbench that includes the extracted .cir file

The annoying thing is that it can't be automatic because the extracted parameters to the top level LVS extracted subcircuit periodically changes which means I have to hand edit (or check) the instantiation each time rather than just running ngspice.

So my suggestion is that klayout sort the ports of subcircuits alphabetically - either every extracted sub circuit, or just top level one (that is not referenced by other subcircuits in the output file).

Alternately you could keep the parameter order from the spice deck you were running LVS against (that would make it easier to switch backwards and forwards between extracted spice and reference designs) - this is probably more complex to implement, alphabetically would be OK

• thanks

Matthias

You mean parameters or ports?

Ports are not necessarily named in the extracted netlist - if you name the nets by labels, that can be done, but if the nets are not named the nets are numbered arbitrarily and ports can change order. There is no way to ensure a specific port order in the general case. LVS is port order agnostic and that is what the extracted netlist is made for.

The right way to think that is back annotation. The LVS will give you the correspondence between extracted netlist and schematic netlist through the cross reference information. So it is basically possible to create a netlist that is identical to schematic in most respects, but there is a caveat: the hierarchy may be different - i.e. some circuits may be flat in the extracted netlist, so the correspondence can only be established between circuits that are present and matched in both netlists.

If it is just about top level circuit pins, it's easier, because if you use "make_top_level_pins", it will only create pins from named nets.

You can monkey-patch the Netlist class to provide an alternative "make_top_level_pins" which sorts by name. Put this into your LVS script somewhere at the beginning:

class RBA::Netlist

  def make_top_level_pins_sorted

    # gets the top circuit
    top_circuit = self.top_circuit

    # collect the pin information we have so far
    pin_info = top_circuit.each_pin.collect { |p| [ p.name, top_circuit.net_for_pin(p) ] }

    # remove all current pins (note best practice: don't delete while iterating the pins)
    current_pins = top_circuit.each_pin.to_a
    current_pins.each do |pin| 
      # important: first disconnect, then remove
      top_circuit.disconnect_pin(pin)
      top_circuit.remove_pin(pin.id) 
    end

    # regenerate pins sorted by name
    # NOTE: you can implement your own sorting here. 
    # For example to sort without considering case, use
    #   a[0].upcase <=> b[0].upcase

    pin_info.sort { |a,b| a[0] <=> b[0] }.each do |info|
      name, net = info
      new_pin = top_circuit.create_pin(name)
      top_circuit.connect_pin(new_pin, net)
    end

  end

end

In your LVS deck, use this method then to generate top level pins sorted by net names:

netlist.make_top_level_pins_sorted

You can use this call instead of "make_top_level_pins".

Note: puts this method call before "compare" - otherwise your cross references will be wrong.

Matthias