Help with connectivity rules

markdayton

I am trying to define a rule that will check connectivity between layer 18 and layer 3, via layer 14, but only when layer 27 is not present. I tried 18 / 14 / 3*-27 and 18 / 14 / 3*(-27) and a few other ways of writing it, but with no luck. Is it possible to do this, and if so, how?

Matthias

Hi,

The following connection specification should do the job:

Conductor 1     Via           Conductor 2
---------------------------------------------
18              14-27         3 

I have tested this on a simple example.

Matthias

markdayton

Thanks Matthias. It works better than my attempt, but I'm still not getting the results I expect. I guess there is another layer/path connecting the shapes and I haven't grabbed the right one to exclude. Unfortunately I can't get more specific, but thank you for the quick response and for all you have done and continue to do to make KLayout the awesome tool that it is.

markdayton

I do have a feature request that would be a work around for my particular use case, and that would be to add the ability to enable/disable rules in the Layer Stack. This way I wouldn't need two different Technology setups depending on what part of the circuit I'm checking (I could also solve it by getting the Layout group to add a recognition layer shape to new layouts around the problem circuit elements, but that wouldn't help all of the existing layouts I need to review).

Matthias

Hi,

to be frank, I've neved had this request before.

The usual approach is to select different rules depending on additional mask layers. Since the physics of your connection must be somehow determined by the masks in a lithography process, it should be possible to select conductors based on the mask layers.

You have given one example already before: layer 14 is conductive only if 27 is not present. You can do the opposite by using an AND operation (14 is conductive only if 27 is present). It's quite common to have mask combination rules to select areas which are connected or not connected: salicide blocking turns poly into a resistor (basically disconnecting the attached parts), MIM cap marker layers block vias, poly gates separate drain and source area in a CMOS transistor's active area and so forth. Often you deal with design layers rather than mask layers. In that case the layers sometimes are marker layers and do not represent physical structures, but still they may serve as a feature to distinguish the various rules.

In KLayout, you can combine more than one boolean operations to achieve the desired result. Utilizing the symbols you can derive intermediate layers to simplify the formulas. Maybe this feature provides enough tooling to solve you problem?

Matthias

markdayton

Thanks for all your help with this. Where I'm running into problems is in the active devices. Layer 3 is used both to define high value resistors and the active area on devices. Unfortunately they can have identical metal stack ups, so when I click on signal lines the trace net just blasts through the device when I want it to stop where the input/output connects with the device, where layer 3 marks the boundary. You mention marker layers, and on other processes that I have used they have been very helpful, but the process I am using now doesn't use them. I could add markers around the devices, but I am trying to avoid that if possible (mainly because the engineers I am trying to train how to use KLayout wouldn't want to modify the layout in any way to avoid creating or covering over errors). Being able to switch off the layer 3 rule after tracing all the lines with high value resistors, before moving on to signal lines, would simplify things (the user wouldn't have to remember how to reconstruct the rule when it was needed back - currently I'm accomplishing this with two different technology profiles, with & without resistors).

Matthias

Hello,

if I understand you correctly, the same physical material (i.e. n doped substrate) is used both for resistors and for active area as well. That's probably legal but then it's only the dimension that makes a difference between a resistor. I imagine that a resistor is rather a thin, maybe folded line while the active area of a transistor is a single rectangle.

Maybe it's an option to generate a marker layer using a DRC runset?

A technology switch is a major feature change and surely nothing that's done quickly.

Matthias