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Design+DRC in KLayout and final DRC sign-off in Cadence
I would like to do the design and DRC of a chip in KLayout and then have the final DRC for design sign off done in Cadence. The final sign off in Cadence is required by the company fabbing our chip. Would this work?
Comments
If your klayout DRC runset equals the Cadence
(or Caliber, as many "Cadence centric" foundries
use Caliber as the golden tape-in tool) then the
tape-in check should be a "nothing to see" event.
But then somebody would have had to do that
work, building the verification decks.
You'd also probably need to check that all the
Cadence layers have a stream out, stream in
definition (many do not, in standard Cadence
PDKs, yet are essential to the operation of
verification runsets - marker and identifier
layers which have no mask destination.
Now, depending on the foundry, the nature and
purpose of the mask art, come classes of "error"
may be waived through a process of exposition
and negotiation. A product for sale would see a
stricter challenge, than a test chip that's meant
for breaking and testing rules on purpose, or a
grad school chip design project where the
journey is the destination. If you anticipate this
then start early on the triage of "acceptable vs
unacceptable errors" and fixing the ones that
will actually prevent database acceptance.
@mayodesigner My personal experience matches with the previous statement from @dick_freebird
I assume that by "Cadence" you actually mean "Calibre" as most foundries only provide Calibre rule decks in their PDKs. It's not possible to directly read Calibre SVRF decks as this format is protected and KLayout is not allowed to parse it. So eventually someone has to provide a separate implementation of the foundry's rules when you want to run DRC in KLayout.
This usually isn't an easy task, specifically as Calibre is somewhat more powerful than KLayout (at least as of now). But my experience is that it is possible to implement the most basic (and most important) rules is a quick way in KLayout - like width and space ground rules, enclosure, isolation and booleans. Refined rules for manufacturability and design robustness like density or latch-up checks and usually only important when it comes to the final chip assembly.
So it may be possible to use KLayout for quick and frequent DRCs and Calibre in the final assembly phase shortly before you tape out your design. Still, the effort of creating a rule deck remains and challenge.
Matthias