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I want to check the number of Via's connecting wide metals.
In case of only 1 via, it will pass clean LVS and DRC
I want to check that on each intersection between M1 and M2 that are wide metals, there will be enough Via's that will cover all the intersection.
Best Regards,
Beny
Comments
You should be more specific on the term "enough". How exactly do you define you pass or fail criterion?
Matthias
Usually, all the area should be covered by Via's. It's depend on the metal width and the DRC rules for each Via. I will modify the numbers after that according the Design rules.
the problem is, that if the designer put only 1 Via there will be leakage issue but LVS and DRC will pass.
I hope I manage to explain.
Beny
I have never seen such a rule, although it's in the category of
"why wouldn't you?". In my world however the design of fat
bussing proceeds from analysis of current density for
reliability, and ohmic drops for parametric performance
leading to a drawn W for conductors and a patch of N vias
(J*K array) similarly figured from rules and simulation or
hand calculation results. All semi-manual.
Now as to implementation, you could (I expect) derive the
layer-intersection area polygons, and scrub them against
an oversize of the interlayer via (+ 1/2 space rule) and then
ANDNOT. Leaving little "gap polygons if vias are spaced more
than minimum, and bigger ones if omitted / few.
As an anecdote I have worked in technologies where
large via beds have an issue with -too high- density. This
would not happen in a CMP, tungsten plug via flow but in
a hot aluminum process where via is filled by metal from
the upper layer, that steals material from the layer and
multiple vias have to "fight over the pie" leading to step
coverage and even bottom voiding inspection / reliability
issues. In this case we figured the large-bed via spacing
needed to obtain ideal via filling, and had one of our CAD
people make a via density script which would "reform"
large via beds identified in the layout. This latter suggests
a way to fix, rather than simply flag, "light via count" errors.
@BenyBar
Hope this will been helpful
Thanks for your replay guys,
This was very helpful.
I will write something and will publish if it works.
Thanks again,
Beny
I have seen companies using scripts to check for empty intersections of neighboring metals, and filling them with vias.
Obviously, this goes one step beyond just checking the missing vias.
Whether that is enough or not, and what's the criteria for "enough" (resistance? EM / current density? Thermal resistance?...) - is a whole different question, requiring you to perform more detailed analysis and verification.