dick_freebird
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This might be a use for a "cutter" feature, a path or polygon that would ANDNOT with things coincident for extract logic purposes only? Like for occasions when "connect" logic connects things you didn't mean to and breaks device…
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If properties are a thing, albeit unused, I'd like to see some thought given to how they could be. Perhaps a few properties like 'instanceName' would be big levers. I certainly do like using instance names as first guess for correspondence. And i…
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You might make this easier by "baking in" features to the pad layout cells or PCells. A placed-by-construction text is easy to grab origin, of. If you made the text value inherited (is this possible?) you might even get padName tied to P…
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I've seen some tools which have select-direction modality and I try to turn it off, first thing. Same with "strokes". Too much conflict with "muscle memory" from simpler times. Now I would be in favor of more modal options in s…
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I don't know nuthin' from scripting but are you sure that instances and layers are "valid"/ selectable, either as a default on startup / layer-gen-from-readin or asserted? Is "one" object selectable under same "preamble&qu…
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I think I'd begin (presuming this is an ASCII techfile) with finding and inspecting the flagged line for odd qualities that the import might choke on. For example Brand X is prone to be verbose and long- winded, and the line might exceed a baked i…
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While I'm wishing for installation ease, how about a script or even a simple list of all dependencies? I've installed klayout to fresh Linux installs a dozen or more times and always end up chasing packages, fail-message after fail-message until d…
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I looked at an openaccess pdk and it sure seemed full of proprietary data format stuff to me. Not sure how "open" it really is. Other than branding. Streamin to a Cadence database format or an "open" format has nothing to do …
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I always have trouble navigating git and finding the right thing to download, unless I have clear simple instructions about setting up the git image (?) and pulling. I can't find that, specifically, in the doc-chain. It would be a good addition to…
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I'll note that in real process lithography there is often a mask sizing applied at mask fab paperwork time, to return an on-wafer feature CD that is as-drawn, based on known lithography error (PR develop, over/under-etch, etc. all stack up per la…
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This is one area where "asserted" recognition and connect- targets might be superior to logical recognition. Not that this is available here and now, on this DB. I believe the deal is "merging gone too far" (or too flat). But q…
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Hi Matthias, Has there been any documentation of this function, with emphasis on DRC scripting (examples?)? Connectivity by tagged polygons too? Parametrics like LF, WF, NF, M (for MOSFETs) by text or by "measure bars" on special (non-mas…
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I disagree with the "top level has no pins" statement. Every one of my Brand X designs, I put pins on the pads - best way there is to assert top level connections and give LVS a "running start" at it. And the top level schrmati…
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Seems this techfile import script has either gone missing, or has some sort of protection that regular users can't get past now: Forbidden You don't have permission to access this resource. And just when I had a real good use for it too.
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Why does extracted not find the ind_in naming? Pin missing, wrong layer, ...?
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Maybe you could say just what "correctly" is supposed to mean. Layers with no content will "act funny".
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Might have to do with vertices / origins snapping-to-grid? There are some options about how that acts. Non-manhattan rotations stand a good chance of putting something off-grid. What happens then, depends on settings.
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Curious whether the klayout LVS understands pin-permute and has support for permute rules for pins (which ones can swap - like regular MOS would always have permuteParallel rule for S and D, but an asymmetric (drain-extended / annular / LDMOS) wou…
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Two problems (or more) I think. First the NAND gate needs to be botom-up correct all by itself. Seems that's not the case (initially at least). Then if higher level assemblies mis-follow the connectivity and call a pin-swap, that must then be a…
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Earlier in the thread the desire for a PDF report got as far as sending to printer, not file. But at least on the Windows side "Save to PDF" and "Microsoft Print to PDF" are pretty much universal options. But tending to appear…
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I sometimes have a need to go the opposite direction, like taking packaging house cavity drawings in to the layout for making bond figures.
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Let me suggest that generating the "numbering" might be better off as a separate exercise divorced from the hierarchy. Like, determine the "placement grid" for texts, make a routine that indexes content along with setpping coor…
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This looks more like a layertable, I like it. Probably a better thing for PDK which wants to control what layers are and aren't picked up from a layout (no auto-add or multiple entries sharing layer & purpose generated by opening a file). Are …
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One neat thing about Brand X texts is the "draftingP" property option, which will cause a label to always show right side up (horizontal) or top side to the left (vertical) regardless of axis flip / rotate stackup through the hierarchy o…
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If you know -why- the device is "faulty" then I'd presume you could write a regular DRC rule to highlight the feature. Of course there are many ways to die, and you may find that this will "churn" your DRC deck ongoing as disc…
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I think about Partial-Select and that selecting a single vertex might be able to deliver the nearest-neighbor coords somehow, to figure the angle of it?
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I have a question about this: (Quote) This would seem to preclude a central reference library, or users would have to copy local (not happy-making for those who manage). So... * can a symbolic link in ~/.klayout/libraries work? See remark about …
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$20/hr? How Wal-Mart of you. A professional IC layout person probably sees 5X that. My lawn dude gets $30. Of course he's got a mower to feed. So probably depending on the kindness of strangers. Might start at the start and declare your approach,…
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I do analog ICs (if I'm asked to do digital, it gets done transistor level and SPICE verification). I never use a SPICE deck to drive layout, schematic speaks to me and I lay out from that view. A custom SPICE model set for LVS (dropping all para…
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So when you click Macros>Macro_Development (F5) nothing happens? Current release is 0.28.7 (or, that's the last time -I- updated...).