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Seems that the GDS-format layout tools don't provide the same ability to reference multiple cell libraries in layout. For example there might be a foundry's ESD / I/O library, a "core devices" library, maybe some digital, analog, RF macrocell libs and then the user's collection of art (common cells and mask-set-specific chip layout, which might have several for whatever design management reasons.
I've been evaluating another ($$$) tool that shows this as a significant (to me) limitation.
I'm not seeing anything that looks like it touches on this, in the discussions Search. Maybe I have to read the manual. But I'd be interested to hear from anyone doing full chip design with a high mix of libraries and providers, how what's possible / practical in KLayout compares to what you can do (rack 'em up and pick, ala carte) in commercial tools like Cadence Virtuoso and Silvaco Expert (where they "own" the native format, comprehend the external filesystem and are not constrained by the fact that GDS-II is kinda dumb about external "stuff").