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Thinking ahead to trying to LVS something, I am curious about device recognition. I have a plurality of different NPN transistor layouts - lateral and vertical, with and without collector ring, etc. Fewer PNPs, but several styles - lateral, substrate. My question regards the facilities for assigning the netlist model to a "found device instance". Unlike vanilla CMOS where there's two device types varying only in W, L, M, here I need to assign the correct model to a device which may vary by features, but not in a very nice "boolean logic friendly" way.
In a previous life I worked with similar issues, but Cadence Diva extract and DRC both understood a get_texted(shape_layer, text_to_match) function which would let you "tag" any polygon at any level with a text that can define what it's for.
So for example I might want to make a transistor with "NPN_cbe_1X" text inside the "TANK" rectangle, be recognized and its model assigned to "NPN_cbe_1X" SPICE model, while another with a ring collector and different layout has "NPN_rceb_1X" and would see the model reference for "NPN_rceb_1X" written to the netlist instead.
Very much easier than trying to express by Boolean logic whether the device has or has not the ring collector, the order of its emitter and base contacts relative to collector(s), the size and so on. Does such a capability exist? I gather that the LVS (connectivity extract) is somewhere in the development phase and documentation, probably further back in the weeds. I did not find more than a half-page description of connectivity with only the simplest operators mentioned.
If there is a function that works like this I'd like to know where to find primers / manuals / anything about it.
If there isn't, I'd like to encourage its addition to the extract / DRC toolbox; it's also handy for applying device-specific layout rules.