Ambiguity resolution issue in LVS

Hi, Matthias,
As you may know, ambiguities occur in highly parallel and symmetric circuits.
For example, if there are placing decap cell (consists of PMOS/NMOS )between VDD and VSS,
those decap cells can be interchanged without affecting the connectivity.
Then, it is impossible to distinguish between the such cells.
When I tried to run LVS for my existing hand-crafted logic circuit block including 360 of decap cell, matching was failed at top level connection.

To confirm this issue, I made simple test cell and tested LVS.
The cell consists of 1 of INV cell and "n" of Decap cell (2PMOS+2NMOS) between VDD and VSS.

Result was as follows;
n < 22 -> Matching completed.
n >= 22 -> Matching did not complete.

Is it possible to enlarge this N by enhancement?
Thank you very much in advance.

---- netlist -----
.subckt TEST Z A VDD VSS
Xdecap[21] VDD VSS DECAP
Xdecap[22] VDD VSS DECAP
.ends TEST
---- netlist ---------


If you solve this issue, Klayout's LVS functionality will become similar to commercial tools.
So far you have appreciated the many enhancements needed for LVS in stand cell base logic circuits.
(Dummy poly pin, Double height cell, Reduce split gate, etc.)



  • edited March 4

    Hi haru_f,

    There is such a limit, but you can increase it. It's called the "branch complexity". The LVS compare algorithm is a backtracking algorithm and the branch complexity is the number of branches tried to achieve a matching. The maximum branch complexity is to safeguard the algorithm against runtime explosion.

    The default value is 500 and with 23 DECAP cells the number of potential combinations is 23 (extracted) x 23 (schematic) > 500. I hope increasing the branch complexity will not increase the runtime accordingly ... if it does, then I need to optimize this case.

    You can set the maximum branch complexity to 10000 with


    In general however, the best strategy IMHO is to turn the DECAP cells into single caps and combine them into one. The path to this solution is to flatten the DECAP cell (I assume it has a single cap inside). After this, the device combination step in "netlist.simplify" should reduce these caps to a single big one.

    Kind regards,


  • It would seem to me that this particular situation would
    be solved by "permute parallel" (aka "device reduction")
    MOSFET rules, as the decoupling caps are all entirely parallel?
    Should "decompose" into one MOSFET (cap) of N fingers?

    Of course such rules need to be populated and invoked for
    the technology.

    At one place I worked we had a CAD person create a Perl
    script that would comb Spectre netlists for paralleled FETs
    and combine them to a

  • Hi Matthias, dick_freebird,

    Thank you your your advice and comment.
    By adding "max_branch_complexity(10000)" , improvement was confirmed at a small test block.
    Unfortunately, my target block still did not match.
    Then, I flattend the DECAP cell by 1 level and matching was completed.


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