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Question first: How can I perform an LVS check of MOS transistors while treating fingered devices as equal to combined devices?
A while ago I started using KLayout LVS for verifying the output of the LibreCell standard-cell generator. Now I'm stuck with the following easy problem: The extracted netlist seems to have devices combined, while the reference netlist has not. This makes the LVS check fail. I tried to
simplify() the reference netlist. But this has no effect while on the extracted netlist this works. (Maybe because S/D don't match in the reference netlist?)
A working solution is to not combine the devices in the extracted netlist. However, I would like to find a more generic approach because the layout generator may or may not decide to split or combine transistors.
This is how the netlists look:
LVS extracted netlist: circuit INVX4 (A=A,GND=GND,Y=Y,VDD=VDD); device PMOS $1 (S=Y,G=A,D=VDD) (L=0.05,W=2,AS=0.45,AD=0.3525,PS=4.9,PD=2.75); device NMOS $3 (S=Y,G=A,D=GND) (L=0.05,W=1,AS=0.20125,AD=0.20125,PS=2.325,PD=2.325); end; LVS reference netlist: circuit INVX4 (VDD=VDD,GND=GND,Y=Y,A=A); device PMOS '0' (S=Y,G=A,D=VDD) (L=0.05,W=1,AS=0,AD=0,PS=0,PD=0); device PMOS '1' (S=VDD,G=A,D=Y) (L=0.05,W=1,AS=0,AD=0,PS=0,PD=0); device NMOS '2' (S=Y,G=A,D=GND) (L=0.05,W=0.5,AS=0,AD=0,PS=0,PD=0); device NMOS '3' (S=GND,G=A,D=Y) (L=0.05,W=0.5,AS=0,AD=0,PS=0,PD=0); end;
Here is the layout:
Thanks in advance!