JFET model - 4 terminal? symmetric?

edited July 17 in Verification

This time I have a question to you ... :)

I want to implement a JFET model for netlisting. My reasoning is that JFET is basically just MOSFET without gate oxide. So the basic geometry model should be the same. But I have no experience with JFET devices.

In MOSFET there is some variety however: DMOS for asymmetric MOS (typically found in DMOS devices), plain MOS for symmetric transistors and the 3/4 terminal versions - 4 for standard bulk devices and 3 terminals for SOI and similar cases.

Question: does one have similar variants for JFET too? I noticed that in ngspice and LTspice, there is only a JFET model with 3 terminals. Does that mean a JFET will never have a bulk terminal? And does one need to differentiate between symmetric and asymmetric cases? And if so, what's a good name for asymmetric and symmetric models?

So far I'd go for three terminal devices only and "JFET" would be asymmetric always. This would make device extraction more difficult as source and drain need to be differentiated - e.g. by a layer marking drain or source.

Thanks,

Matthias

Comments

  • The PJFETs I have used, used a simple bar of emitter (N+)
    across the channel implant, and its ends, outside the
    channel stripe, contact the collector region. So although
    the front and back gate are separate they are electrically
    common.

    In a JI technology there would potentially be a "bulk" node
    with a diode connection. My work with JFETs was all in
    dielectric-isolated technologies.

    I only saw symmetric JFETs. It's not clear to me how you
    would add asymmetry to a JFET, or why. Maybe a field plate
    kind of thing?

    I might be able to find some example layouts but can't claim
    they represent the device-design-space, only portions of it.

  • Found an example layout for a 40V PJFET. There is an
    asymmetric field plate feature. If I can find your email I'll
    send you the .gds and layer assignments.

  • As it happens, one of my chips under design right now
    uses a "Epi FET" for a bias current feed, and this is not
    like any explicitly designed, gain-element JFET. It is just
    a region of N-epi pinched between two ISO (P+) bars,
    running nearly the height of the chip and stacked on top
    of a NPN (whose collector is also the N-epi region in
    question). The whole subject of old-timey analog JI
    layout and the clever shortcuts used, how to pick off the
    individual bits is also on my mind.

    But here's the "Epi FET":

    It's a real crappy JFET used in IDSS mode as a high value
    pinched resistor more or less. But there is no front gate,
    just the lateral pinch of ISO into TANK (N-epi).

    An ability to recognize this style of FET, and maybe also to
    pick up pinched resistors (call them a JFET, which they are)
    would be great.

    I can provide you layouts of these critters
    as well, if you let me know where you'd like that to land.

  • Wow! thanks a lot. That's almost too much to digest :)

    My initial trigger was the HEMT FET discussion in this forum. This one is a symmetric device, but I'd need a JFET model simply to be able to print it to SPICE.

    I think I get an impression of the pics. Although I'm still impressed by the ingenuity of the old days, I'm afraid extracting "optimized" devices is probably asking too much from a simple stupid device recognition algorithm such as mine :(

    But thanks for the pinched resistor hint. Model-wise that can't be a resistor, so it make sense to support this through the extraction model. I just don't know how to recognize them without gate. That's the boolean marker for the channel region.

    Asymmetry I simply provide by having individual inputs for source and drain - for symmetric models, there is only one input and device recognition takes one side of "gate" to be drain and the other side for source. But you can't say which is which and the symmetric device model also needs to say the source and drain can be swapped during LVS.

    You can send layouts to contact @ klayout . de if you want.

    Thanks and best regards,

    Matthias

  • edited August 3

    Hello all,
    as far as I know most silicon JFETs are symmetric. As dick_freebird already mentioned maybe for high voltage applications this may not be the case. For JFETs/HEMTs I do not know about any model that takes gate length (or width) into consideration. Most models work with values for transconductance and capacitance. Maybe a workaround would be to calculate the gate capacitance which scales with width/length. Therefore a connection check and a DRC maybe the way to go. I think the most common JFET model is the one derived from Shichman and Hodges LTSpice-JFET Model. A MOS transistor without bulk. There are other models for GaAs-FETs like TOM3, Materka, Statz, but I think for the simple "is the device connected properly" the Shichman and Hodges model should do a reasonable job.

    I think another problem is that JFETs can be done in many ways.
    one (classic way): channel sandwiched by top and bottom gate (gates shorted or not)
    or vertically like this one from doi: 10.1109/TIA.2010.2090843

    Best Leo

  • This all leads me back around to my desire for an
    "assertion based" extraction (as opposed to a logic
    applied to an assembly of shapes).

    A boundary polygon tagged with device-type text,
    and pin features (e.g. contact) tagged with pin-name
    text, and you're there. With maybe a backstop logic
    that flags devices not-so-tagged as invalid.

    Of course there is a need for ability to extract layouts
    from elsewhere, which could lack these features
    unless somebody went in and did the work at the
    device-primitives level. I'm not disparaging the existing
    and developmental extractors, only recognizing that
    a "do-all" recognizer logic may be impractically large
    (consider the fun of working in a technology with 4
    VT options times non-, drain, double-extended options
    times two Tox, straight and annular and ringed-source
    and H-gate, and that's just for the NMOS). So much
    easier to assert what it is, where it hooks up, if you
    are building a primitive device library and rules for
    yourself.

    I know it's doable. Too bad about the skillz deficit
    at this end.

  • Thanks for all your inputs!

    @dick_freebird The assertion-based extraction would be my last resort. I know this is thin ice as some users will regard that highly risky and heresy against the teaching of agnostic LVS. But for some devices such as coils I don't see an alternative. Technically I think tagging should already work with the help of "with_text" and maybe some more operations.

    For the layouts I get most of the time I don't have access to a device library. Often those are streamed out Cadence layouts and their PCell substance is not accessible for me. I for myself have to live with the polygons I get :(

    Best regards,

    Matthias

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