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This time I have a question to you ...
I want to implement a JFET model for netlisting. My reasoning is that JFET is basically just MOSFET without gate oxide. So the basic geometry model should be the same. But I have no experience with JFET devices.
In MOSFET there is some variety however: DMOS for asymmetric MOS (typically found in DMOS devices), plain MOS for symmetric transistors and the 3/4 terminal versions - 4 for standard bulk devices and 3 terminals for SOI and similar cases.
Question: does one have similar variants for JFET too? I noticed that in ngspice and LTspice, there is only a JFET model with 3 terminals. Does that mean a JFET will never have a bulk terminal? And does one need to differentiate between symmetric and asymmetric cases? And if so, what's a good name for asymmetric and symmetric models?
So far I'd go for three terminal devices only and "JFET" would be asymmetric always. This would make device extraction more difficult as source and drain need to be differentiated - e.g. by a layer marking drain or source.