How to deal with conflicts during simplify in LVS?

After the align and simplifiy, the device will be combined. Therefore, many resistors or transistors connected in parallel or in series will be reduced to one device. Sometimes, this leads to difficult matching between the extracted netlist and the original netlist, because sometimes series resistance will be recognized as a whole resistance, which is obviously wrong, but sometimes some of the same series or parallel resistance needs to be simplified.
What should I do in this case? How can I set a global or local simplify?


  • I occasionally have to go back to the schematic
    and update the length and segments properties
    to reflect the "observed layout reality". This would
    be one of your your "local" options, appropriate if
    the schematic reflecting as-laid-out makes the

    Asking "should be same, but different details"
    to be figured out 100%, may be too much to expect -
    even $$$,$$$ tools with professional grade PDKs
    will stumble on occasion.

    There's no shame in schematic realism.

  • @dick_freebird "Schematic realism" - I like that :)

    @Bian Would that be a decision based on the device class (model) or does it need to be an individual decision based on each individual instance of a device?

    In the next minor release (0.27.3) you should be able to turn off combination modes on device classes basis like this:

    res_cls = extract_devices(resistor, ...)
    res_cls.supports_parallel_combination = false
    res_cls.supports_serial_combination = false


  • edited July 2021

    @Matthias Based on this individual instance.

    I want to compare a macro composed of many identical resistors connected in series. The netlist reader recognizes it as many individual resistors, but after simplifying, only the simplified resistors are still displayed, so I wonder if I can solve the problem by turning off some of the simpler.

    How should I deal with that?

    This Res5 is a part of a large circuit. To make the problem easier, I've redesigned this bug. The following is the test file.
    Sincerely thanks for your Help! :)

  • Maybe, you can try to simplify the schematic netlist as well :


  • @laurent_c Thanks! That works very well, I didn’t know method .simplify would work for the schematic too :D
    But now I've found a new bug, can't simplify multilevel call macros.
    For example, re1 is composed of 6 resistors and re2 is composed of 9 re1s. After schematic.simplify, there are nine re1 in the reference netlist. This Macro is not completely simplified.

    Is it possible to completely simplify multi-level call macros? Or is there any other way to deal with it?
    The following is the new rebuilded Bug.

  • edited July 2021

    @Bian Device combination across hierarchies is not supported, but you can flatten the RES1 and Res1 subcircuits:

    connect(met1_dg,      cont)
    connect(p1trm,        cont)

    BTW: if I use the sheet rho from the schematics (a 5 squares resistor has 1565.15 ohms) like this:

    rpp1 = extract_devices(ResistorExtractor::new("RPP1", 1565.15/5), 
      { "C" => p1trm, "R" => rpp1 })

    even the resistor values match and I don't need the DeviceComparer:



  • @Bian I noticed one detail which is actually rather non-intuitive and I'm considering the change that. But in your case it would help getting rid of the DeviceComparer.

    If you specify a tolerance, only those parameters with a tolerance are considered.

    In your case if you use:

    tolerance("RPP1", "L", 1e-5)
    tolerance("RPP1", "W", 1e-5)

    will ignore the "R" parameter.

    This is unexpected and I'd rather change that to "the other parameters are still compared using the default rule". In 0.27.3, you can disable or enable parameters for being included in the default compare scheme.

    I have created a ticket for this and I'm open to discussion here:


  • @Matthias
    Thanks for your answer. That is the point I mentioned last time
    Because if the size of the resistor is very small, the actual resistor value cannot be estimated by simple calculations. The exact value of sheet_ratio will vary with the size of the resistor. If the size of the resistor is small, it obviously has nonlinear properties.
    Therefore I only chose length and width as comparison parameters. This is also inspired by the caliber. Its default mode only compares length and width of resistors. To make sure the correct comparison result is obtained, I only compare length and width.
    I don't know how others do this, which parameter they compare to make sure the consistency of resistors between layout and original circuit. Is the verification through the resistance value more authoritative? Although the edge effect of the resistance makes it difficult to accurately estimate the resistance

  • edited July 2021

    I don't like the resistance value. Another reason is that the value of sheet_ratio I found in the process file itself is variable and complicated.

    I used to think that ignoring of the resistance value is the special setting you answered last time :D

    I think your idea is really great.
    The second method in github you mentioned looks concise but it should be difficult for users to notice this tip by reading the documentation.

    But in fact, through communicating with you, I can now correctly achieve my verification goal.

    Looking forward to the next version and sincerely thanks! :D

  • @Bian I have implemented the suggestion from GitHub already, but in a slightly different way.

    My reasoning was that "tolerance+ignore" is a little weird for a concept, so there is simply an "ignore_parameter" feature.

    Your test case passes with this update:

    tolerance("RPP1", "W", 1e-5)
    tolerance("RPP1", "L", 1e-5)
    ignore_parameter("RPP1", "R")

    And the custom comparer is no longer required.

    Best regards,


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