Why "deep" in DRC script doesn't make function?

edited September 29 in General


I recently find "deep" in DRC script doesn't make function, it still show errors in flat.

The script are as follows:

report(" DRC report.lyrdb")
dummy_check = false
DENSITY = false

HMWG = input(1, 0)
SLABWG = input(2, 0)
STRIPWG = input(3, 0)



SLABWGe.enclosing(STRIPWGe,2.um).output("SLABWG.E.SITRIPWG.01.OVERLAY", "Optional--Minimum inclusion of SITRIPWG in SLABWG layer in rib waveguide=2 um")

(STRIPWGe-SLABWGe).output("SLABWG.E.SITRIPWG.02.OVERLAY", "Optional--SITRIPWG layer larger than SLAB layer is not allowed in rib waveguide")




f.output("HMWG.E.STRIPWG.OVERLAY", "Optional--The STRIPWG layer cannot exceed HMWG waveguide in the tip,the space should be more than or equal to 0.05 um.")


The gds file are shown as follows:

After run, it shows errors like this:

I guess that is why it runs slowly for large layout. Every kind of errors consumes large space, and the number of one kind of error could be up to 2000000. So I can hardly get the final drc results.

Is there a good way to solve this?


  • @Weiling_Zheng "tiles(1000)" will turn off "deep" (see here: https://www.klayout.de/doc-qt5/manual/drc_runsets.html#h2-1028). Comment out "tiles(1000)" or move "deep" after it.

    But I have a stupid question maybe: who wants to have a DRC which reports 2000000 errors? A DRC is supposed to give 0 errors - at least for a clean layout. If you want to produce such a number of results, consider writing the output to a layout layer. The report DB isn't made for millions of errors.

    And deep mode is no warranty of getting a DRC faster. The hierarchical analysis may take longer than a flat DRC.


  • @Matthias ,

    Thank you very much for your respond.
    Using tiles(1000) could speed up verification,right?

    I see the possibility of increase in verification speed by using the method you said, "writing the output to a layout layer" . I will check the running time further.

    For me, the report of 2000000 may happen when there are a lot of error in one kind of vertification in flat DRC. It can also happen when a lot of mismatch waveguide for a large layout.
    Or, there are a lot of angled shapes in the pattern.

    I may sort out the specific problems of DRC encountered during operation in the future, which are mainly reflected in the operation speed and the accuracy of DRC inspection. I will seek for you help when the time comes.

    Thank you again.

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