LVS: check connection and resistance of multilayer via chain


I asked the same question here and unfortunately didn't understand the answer.
So I would like to check the connection in so-called via chain structure to be sure that there are no opens (via or metal planes missing). I also would like to calculate the resistance of all layers (including vias).

Roughly the schematics depicted below

I can't understand how to tell the resistance model that all layers are connected between each other. The connect function didn't work for me.


  • edited November 7
    Tungsten plug vias can dominate net resistance. Don't know if parasitic R extract deals with vertical via resistance or only in-layer l/w*Rs. If not then you may need to make the via a "device" that will cough up the R. Breaking one net into many, alas.
  • Of course the simple example layout shown would be easier to measure, count and calculate than to code the infrastructure....
  • @anatolyb So you didn't mention that you are looking for the resistance of a periodic via chain. This is a typical yield or reliability test structure, not a resistor you would usually use in a design.

    First of all you need a way to tell wiring from resistor "devices". Vias are usually used for providing the connection between two metals. These you don't want to extract as resistors. So you need some kind of marker layer which you draw over the via chain to mark this area.

    But as @dick_freebird mentioned, you need to indicate how your resistance is computed: will this be dominated by the single via resistance (so proportional to the number of vias traversed) or is so you need to take into account the wire resistance too?

    The final solution depends on this model. If the via resistance dominates, a potential solution is to extract single vias as resistors and let the netlist reducer join parallel and serial via "resistors" into the final one.


  • edited November 11

    In case you go for the "dominant via" solution and to provide an educational example for a custom device extractor, here is a solution.

    The basic problem is that KLayout does not offer a "vertical resistor" by default, but we can add that type using a custom device extractor.

    A sample layout is attached. It features two metals, a via and the discussed marker layer (4/0):

    The corresponding LVS script is this:

    report_netlist # input layers m1 = input(1, 0) via = input(2, 0) m2 = input(3, 0) res_marker = input(4, 0) # A custom device extractor example # supplies a new device extractor for resistors: the "vertical resistor" class ViaResistorExtractor < RBA::GenericDeviceExtractor attr_accessor :res_per_area # Constructor def initialize(res_per_area) self.res_per_area = res_per_area end # Configures the extractor # (NOTE: this method is called by the system, no need to call it explicitly) def setup = "ViaResistor" model_name = "via_res" cls = RBA::DeviceClassResistor::new = model_name register_device_class(cls) define_layer("b", "Bottom metal layer") # Index 0 (first) @b_layer = 0 define_layer("v", "Via layer") # Index 1 @v_layer = 1 define_layer("t", "Top metal layer") # Index 2 @t_layer = 2 end # Defines the shapes that connect to form a device # (NOTE: this is not a physical connection, but a logical clustering) def get_connectivity(layout, layers) # NOTE: this is a brief implementation which does not check whether # via is covered by metal or not. Hence, metal shapes are not considered # as part of devices and do not show up in the cluster definition conn = RBA::Connectivity::new conn.connect(layers[@v_layer], layers[@v_layer]) # join via parts return conn end # Extracts the devices def extract_devices(regions) via = regions[@v_layer] via.each_merged do |v| via_area_in_square_um = v.area * self.sdbu * self.sdbu r = via_area_in_square_um * self.res_per_area device = create_device() device.set_parameter(RBA::DeviceClassResistor::PARAM_R, r) # provide the device terminals to connect the metal to later define_terminal(device, RBA::DeviceClassResistor::TERMINAL_A, @b_layer, v) define_terminal(device, RBA::DeviceClassResistor::TERMINAL_B, @t_layer, v) end end end # split via into "normal" and "resistor" vias (res_via, other_via) = via.andnot(res_marker) # build the normal connectivity connect(m1, other_via) connect(other_via, m2) # extract the via devices extract_devices(ViaResistorExtractor::new(1.0), { "b" => m1, "v" => res_via, "t" => m2 }) # build the netlist and combine the resistor devices into single resistors # for the via chain netlist.combine_devices

    The script lacks the schematic input and compare steps, but it extracts and displays (because of "report_netlist") and netlist.

    Small disclaimer: the "combine_devices" step will join all via "resistors" even if they belong to different "islands", like here:

    A solution to this problem is to put the "islands" into separate child cells.

    If you need a more elaborate solution, you can essentially consider everything inside a single marker "island" one device, pull all the shapes into the device extractor and code the via chain assembly and resistor computation yourself. But I think that is not an easy task to code.


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