Extract resistor issue

dai

Hi @Matthias ,

I'm not sure this is a bug or not. I have a rectangle via , I extent two opposite edges to make it become two terminals of resistor. But when i extract i got error.

Here is my script :

deep
report_lvs

# -------------------------------------------------------------------
# Layers
report("DRC")
# Drawing layers
via = polygons(51, 70)
connector =  via.edges.with_angle(0).extended_out(1.dbu)
connector.output("Connector")
extract_devices(resistor("Res1",1),{ "R" => via,"C" => connector })

puts netlist.to_s

I attached gds also.

Thank you,
dai

Matthias

Hello @dai,

thanks for this perfect test case. I'll investigate the problem. Looks like a general problem with extended and related functions in deep mode.

I have created a ticket for this: https://github.com/KLayout/klayout/issues/1190

As a quick workaround I can offer:

connector = via.sized(0, 1.dbu) - via

I have a general remark though: if you use "with_angle(0)" (or the workaround), you basically create a anisotropy which will render cell variants in deep mode. This means that the same cell is handled differently depending on whether a cell is used rotated or not. You may therefore see the same cell popping up multiple times.

There is no quick way to avoid this. I understand for you it is just important to create markers on opposite sides of the via, but they do not necessarily need to be horizontal, right?

Matthias

dai

Thank you, @Matthias

My connector should be on short edge of via if shape of via is rectangle(this relate to value of resistor). If it just square then don't need to care it is horizontal or vertical.
connector = via.extents(0,1.dbu)
it works also.

dai

dick_freebird

Not knowing your technology's constraints, is a non-square,
non-single-allowed-size via supported by the technology?
Not the case, in most advanced lithographies. I don't think
I've seen "freehand" vias allowed outside old timey bipolar
flows and >1um CMOS.

Just wondering whether you're creating challenges that
would "go away on their own"....

dai

Hi @dick_freebird ,
I'm not sure i understand all your thing.
the technology i doing with just support two type of via( square(32x32), rectangle(32x80))
In this case i just want to flag to @Matthias about the error.
I trying extract resistor of specified net (net with multiple layer, multiple via on it).
The way i doing is:
1 .Divide metals polygon into squares and extract each square into a resistor and call it is "metal_resistor"
2. Extract each via into a resistor(connected to null) and call it is "via_resistor"
3. Specify metal_resistor need to connect to via_resistor.
This is all things i thinking and doing now. I don't know if have any better way.

dai