split_gate for netlist object

Hi @Matthias
I saw "split_gate" feature(let us reduce gate) in klayout new version. It is very usefull :).
I think it will be more usefull if we have this feature in netlist object also. Because schematic designer use multiple factor like below some time:

So if we use split_gate for netlist so we need run this feature for netlist of schematic also.

Thank you!


  • edited January 2023

    Well crafted SPICE models will give you different (subtly)
    outcomes from (say) a 100/0.18 and a (10)10/0.18 FET.
    Your verification ahould not ignore or obscure this if any
    analog matching interests are involved. Probably want to
    make this a "switch" in the LVS (where you can decide
    whether or not to allow) rather than in the extract, where
    it may get "baked in" but invisibly so.

  • Hi Jim,

    "split_gates" is not available for schematic, but you can easily add this feature:

    # Somewhere beginning of LVS script def split_gates_on_netlist(netlist, device_name, circuit_pattern = "*") dc = netlist.device_class_by_name(device_name) if ! dc raise("'#{device_name}' is not a valid device name") end if ! dc.respond_to?(:join_split_gates) raise("Device '#{device_name}' is not a kind supporting 'split_gates'") end netlist.circuits_by_name(circuit_pattern).each do |c| dc.join_split_gates(c) end end ... # Use it on schematic: split_gates_on_netlist(schematic, "device_name")

    Regarding extraction (and compare I assume) of the finger ("m") parameter: I think that can be added, but I see a number of open questions - e.g. how to add two devices with different widths.

    Kind regards,


  • Hi @Matthes ,
    It works perfectly

    Thank you,

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