Net check on package level

edited January 31 in Ruby Scripting


I have plowed some LVS related discussions, and envy so much. It's professional and powerful.
I also understand this tool is created for VLSI , but I still wondering if it can do simple check as this one ?

Assume this package structure has 2 metal and 3 di-electric layers ( see attachment ), which redistribute the signal from chip.
Is it possible to create a schematic file like ("check.cir") to alarm if signal mismatch ?

It's ok to let me know if schematic check is only suitable for VLSI , actually I don't know how to generate any XXX.cir file , yet :)
Usually, the metal redistribution route is not complex, but sometimes still got the design from heaven , then require another gate indeed :/


PASSIVATION_lbl = labels(75, 0)
PI3_lbl = labels(95, 0)

connect(PI1, M1)
connect(M1, PI2)
connect(PI2, M2)
connect(M2, PI3)

connect(PI3, PI3_lbl)

( All the pattern in " PI " layer will be considered as " Via " )


  • This is possible, but it needs a few tricks.

    The LVS will basically check topology - this means the way devices are connected to form a functional entity. With your setups there are no devices, so that does not work out of the box.

    But KLayout LVS offers "black box circuits" which are empty circuits with only pins. Such a black box circuit can be embedded and checked against the die.

    So first thing you have to do is to define a cell that represents the die a place some labels where the die pads are. Like this:

    In the redistribution layout you place this cell (we call it "CHIP" here) and add the wiring. The package pads get some labels too. We call this cell "TOP":

    or in full hierarchy view:

    Now, in the schematic you define a subcircuit and the top circuit:

    .subckt TOP
    X1 A B C D E F CHIP
    .subckt CHIP 1 2 3 4 5 6

    in the LVS script we need to tell LVS that "CHIP" is a black box cell ("blank_circuit") and that the names of the top level pads are important: as A, B, C, ... are the same nets topologically, we need to say that we really want to match net A, connecting to pin 1 against net A from the schematic. Same for net B etc. This we do with the "same_nets!" statement. In addition "deep" (hierarchical) mode is important as otherwise subcircuits are not extracted:

    metal       = polygons(1, 0)
    metal_lbl   = labels(1, 0)
    # TODO: further layers
    # "connect" labels and nets (use labels for naming nets)
    connect(metal, metal_lbl)
    # TODO: further connects ...
    # matches TOP net A to schematic A, B to B etc.
    same_nets!("TOP", "*", "*")
    # marks "CHIP" as "black box circuit"
    # boilerplate LVS code


  • edited February 3

    Hello Matthias,

    Thanks for showing me the door :)

    "blank_circuit" trick is great, although this package is die level, but the " black box magic " still workable.
    Please see below image -- part of the package ( I called it " God, forgive me.." design )

    according to its multi input/output feature.. is it possible to set connection relationship not 1 vs 1 ?

    Top A,B,C connect to CHIP 1,2
    D,E connect to 3,4
    then F connect to 5,6

    .subckt TOP
    X1 A,B,C D,E F CHIP
    .subckt CHIP 1,2 3,4 5,6

    It may against VLSI common design concept, and argument limitation for " same_nets " function (seems 1 v 1 only )

    same_nets(circuit_pattern, net_pattern)
    same_nets(circuit_pattern, net_a, net_b)
    same_nets(circuit_a, net_a, circuit_b, net_b)

    This should be ridiculous ? I will update if find something funny, thanks again

    Best regards

  • That is possible, but it needs some explanation.

    "same_nets" cannot do n:m because everything that is connected becomes a single net. So there no "n" or "m", there is always "1".

    Still that is possible.

    First, the downstream case is simple: you declare two pins in the die circuit and connect them to the same net above. These pins are labelled differently in the die cell, so they are identified as separate die pads. In the schematic you use the same net for these two pins. That's it.

    The upstream case (multiple package pads on the same net) is also easy if you notice that labels are additive on a net. So if you place package pads B, C and D on a net, the net gets called "B,C,D". So you need to list the net as "B,C,D" in the netlist and establish the name identity as above with "same_nets".

    Here is my test case:

    So die pads 2, 3 are connected to pad B, C and D. The corresponding schematic is:

    .subckt TOP
    X1 A B,C,D B,C,D E F G CHIP
    .subckt CHIP 1 2 3 4 5 6

    Note that "B,C,D" is a single net name although it looks funny. Note that the pad names are sorted literally, not numerically. So pads "1,2,11,12" form a net called "1,11,12,2".


  • edited February 4

    Hello Matthias,

    Before this, I always outputted netlist.l2n , then some excel job followed
    now I have warrior to guard another door, thanks

    Finally.. passed the test B)

    Best regards,

  • edited April 9

    It's fine 🙂

    @dick_freebird Yes, just as you said, top-bottom verification is doable, that's why I think Klayout is powerful, nice weekend~

    Best regards,

  • If you add all the package construction layers and their
    "connects", and same for the bond wire, then you can
    do an end-end / top-bottom verification.

    Most IC CAD PDKs are single-process and nothing for
    packaging besides (if you're lucky) some plain polygon
    layout views or GDS-II files to import.

    But you could add package layers just like foundries add
    post-fab RDL etc. - if you want to do the work.

Sign In or Register to comment.