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I have plowed some LVS related discussions, and envy so much. It's professional and powerful.
I also understand this tool is created for VLSI , but I still wondering if it can do simple check as this one ?
Assume this package structure has 2 metal and 3 di-electric layers ( see attachment ), which redistribute the signal from chip.
Is it possible to create a schematic file like ("check.cir") to alarm if signal mismatch ?
It's ok to let me know if schematic check is only suitable for VLSI , actually I don't know how to generate any XXX.cir file , yet
Usually, the metal redistribution route is not complex, but sometimes still got the design from heaven , then require another gate indeed
PASSIVATION=input(7,0) PI1=input(1,0) M1=input(2,0) PI2=input(3,0) M2=input(4,0) PI3=input(5,0) PASSIVATION_lbl = labels(75, 0) PI3_lbl = labels(95, 0) connect(PASSIVATION, PI1) connect(PI1, M1) connect(M1, PI2) connect(PI2, M2) connect(M2, PI3) connect(PASSIVATION, PASSIVATION_lbl) connect(PI3, PI3_lbl)
( All the pattern in " PI " layer will be considered as " Via " )