LVS SOI Isolation

yrrapt

We're working with an SOI (Silicon on Insulator) process where we can draw DTI (Deep Trench Isolation) to isolate the bulk substrate.
I am trying to figure out how to include this into our KLayout LVS definition.

Do you have any pointers on how I can describe that if an area of substrate is completely enclosed by a drawn layer, that substrate is electrically isolated from the rest of the substrate?

Thanks in advance

RawrRanger

Hi yrrapt,

Assuming the STI forms a circular shape with a hole inside, the hole can be extract by DRC function `holes`

https://www.klayout.de/doc/about/drc_ref_layer.html#h2-1307

this should allows you to use this gen-layer in LVS
but drawing STI instead of drawing AA is quite uncommon, I rarely encounter situation that requires designers to define transistors by STI.

yrrapt

Thanks for the info RawrRanger,

I'm dealing a partially depleted SOI process with DTI. The STI is indeed handled "automatically" but the DTI is applied selectively by the designer to create isolate tubs. The stack-up looks like this:

Your suggestion helped me in the right direction though.
What I did that now works:
1. Use extent to get the bounding box of the cell and sized() it make it a bit bigger
2. Subtracted the DTI layers to form separate islands of PTUB
3. Connect with ptap to the PTUB islands

Note that I removed all global interconnects of substrate from the KLayout LVS tutorial.

Now I can correctly perform LVS with DTI isolating the substrate regions.

Thanks,
Thomas

dick_freebird

Tub = bulk andnot dti

As you say there is no global psub and all transistor terminals
are connected explicitly.

However use-models for PDSOI vary. On the same flow, I have
seen tub-per-device (which we struggled to do verification on,
in the foundry-provided kit) and tub-per-species seemed the
PDK basis (P tub here, N tub there, wire 'em up). Within a tub
there is still "locally global" Psub / Nwell connection of the
bodies. If you permit a free-for-all design style then you have
to still support the foundry paradigm as well as the tub-per-FET.

If it happens to be CA18HB I'll take a copy of your extract and
LVS decks....

Matthias

Hi Thomas (@yrrapt),

When you create a "outside tub" bulk by using "chip_boundary - dti", KLayout will probably produce a flat netlist even in deep mode. The "holes" approach (dti.holes) may prevent this problem. You should be able to create a cell or macro containing the DTI and the holes will be generated hierarchical. However, in that case you will need to handle the NMOS devices outside dti.holes separately and give the pwell outside dti.holes a global net (I am assuming here that pwell does not have a separate mask, but is everything outside nwell).

Matthias