LVS net matching pins

I am trying to match (align) pins (named nets in layout with text)
to named nets in the netlist, but align ignores that and matches "wrong names" anyway
since pins (PADS really) are not devices, there is no way that i know of to match or hint net names from schematic to layout
in this example I am trying to provoke a mismatch I would like align to tell me that OUTP is connected to OUTN and throw an error.
is there any way I can do that?


  • Hi @heugene,

    Yes, there is. The feature is called same_nets! and is explained here:

    Note that there was a problem with unnamed nets and wildcard expressions, which has been fixed in 0.29.2 (


  • edited June 20

    @Matthias I am having a similar problem where circuits that should not be comparing to true are in 0.29.2 (Mac).

    These are comparing to true, even with "same_nets!("*","*")":

    Extracted Netlist:
    .SUBCKT lvs_test_device$2 ind_in_1 ind_out_1
    L1 ind_in_1 ind_out_1 2n WIRE_IND
    .ENDS lvs_test_device$2

    Reference Netlist:
    .subckt lvs_test_device$2 ind_in_1 ind_in_2
    L1 ind_in_1 ind_out_1 2e-09 WIRE_IND
    .ends lvs_test_device$2

    Edit: perhaps this is because the problem lies in the schematic and not the netlist meaning all the extracted nets have a match in the schematic nets.

    Here is another, worse problem where the problem is with the extracted layout leaving a "floating" internal pin, and compare still resolves to true:
    .SUBCKT lvs_test_device$4 ind_out_1
    L1 \$I1 ind_out_1 1.5p WIRE_IND
    .ENDS lvs_test_device$4

    Reference Netlist:
    .subckt lvs_test_device$4 ind_in_1 ind_out_1
    L1 ind_in_1 ind_out_1 1.5e-12 WIRE_IND
    .ends lvs_test_device$4

    Note: WIRE_IND is a custom device class emulating inductors with other features and has equivalent terminals on its input and output pins. Do you know what is happening here?

  • edited June 21
    Why does extracted not find the ind_in naming? Pin missing, wrong layer, ...?
  • Extracted does not find "ind_in_1" because the label is on the right layer but not over the terminal (I intentionally displaced it).

  • edited June 22

    Hi @cjb_aqc,

    Regarding the first example, is this already the top level circuit? If not, the netlist should not match as L1 is connected in the extracted netlist while it is not in the schematic.

    Top-level circuits do not have pins as there is nothing connecting to them from the outside. It does not matter what pins you declare there. As soon as you embed that subcircuit into another, pins become relevant. For the compare however, only net names matter - pin order or pin names (which are essentially net names) do not. Pins only provide a connection between nets from different circuits. "same_nets!" will only check the for matching nets, both net names are identical, if both nets carry names.

    The use case is to check top-level pad connections, where you have named bond pads and those need to correspond to the same nets in the schematic.


    # extracted
     .SUBCKT lvs_test_device$2 ind_in_1 ind_out_1
    L1 ind_in_1 ind_out_1 2n WIRE_IND
    .ENDS lvs_test_device$2
     .subckt lvs_test_device$2 ind_in_1 ind_in_2
    L1 ind_in_1 ind_out_1 2e-09 WIRE_IND
    .ends lvs_test_device$2

    are the same as topologically "ind_out_1" is the net that connects to the second port of L1.

    Plus, the schematic does not make sense and "ind_out_1" will be a floating net.

    That is the same in the second case, but "ind_in_1" does not correspond to a named layout net, hence no check is made. In a schematic, all nets are named, in a layout usually only some are named (labelled). So unnamed nets are "don't care".

    Bottom line:

  • I disagree with the "top level has no pins" statement.
    Every one of my Brand X designs, I put pins on the
    pads - best way there is to assert top level connections
    and give LVS a "running start" at it.

    And the top level schrmatics all have pins, so why would
    the layout not?

    Now if you can place some other thing to name the
    power and I/O pins, fine. But I like placing pins at the
    center-point of pads.If they perform the net-name-assertion

  • edited June 22

    That requires a kind of pin marker. In GDS there is no pin purpose, so you cannot differentiate drawing from pin. In order to support that, I would need to introduce a pin purpose inside the LVS script.

    Otherwise a pin not different from a wire.

    Right now, every named net on top level is turned into a pin at top level. So rather "pseudo-pins". So essentially, all you have to do is to place labels on the pads.


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