"Floating" layout pins not saved in extracted netlist after netlist.simplify during LVS

barlow

Sometimes, when making hierarchal layouts, you will have cells that contain pins/wires for signals that don't have internal connections to extracted devices. A simple example would be passing a power/ground rail through a gate like a fill cell or maybe a pull-down, but arrayed designs also share these traits. Using the RINGO example, I have a silly pull-down transistor I made out of the inverter cell. Power is on the top, and not connected to anything in the cell.

* Netlist for NFET Pull Down
.SUBCKT NPD VDD VSS IN
M$2 VSS IN IN VSS LVNMOS L=0.25U W=0.95U
.ENDS NPD

Looking at the LVS example script, simplify helps clean up the extracted netlist. This runs purge as part of the cleanup. However, nets with only pins on them (VDD in this case) get deleted. My simple layout puts the tiedown on the output (again, don't think too hard about the schematic). As far as I can tell, this is expected behavior.

The layout nets with only pins get pruned because they have only 1 connection. The VDD net is marked as mismatched because the "VDD" pin of NPD was removed from the extracted NPD netlist. While this example overall shows as "Passing", I had more complicated designs where it would fail (and beside that, I really hate red in my LVS results). I still want to be able to prune nets that don't have any connection (e.g. floating metal/fill), but I don't see how to do that. Do I need to iterate through all the pins and mark them as "dont_purge"?

dick_freebird

There should be prune rules somewhere? But sounds like
you want them applied "surgically"?

Perhaps the rule that does the pruning, could be modified
or enhanced to make a net that contains a pin-polygon (I
guess we don't do that over here, but it's default Brand X
style) or pin-text-label-on-layer not be called a floating net.
Because it's not, exactly - it's got a Z-axis rather than X, Y
axes connection.

Matthias

Yes "surgically" is what is needed here

Here is a counterexample: Think of a via cell - the via has a pin, because it will connect to some metal above on the lower and upper level, It will probably also have two pins.

But I am quite sure you do not want to see via "subcircuits", do you?

Essentially, the idea of "simplify" is to normalize the netlist to some minimum version. That is a version, that preserves the netlist topology without containing irrelevant details. The assumption is that the schematic already has this minimum form.

I'd like to re-phrase the problem here: I think the schematic is not of this minimum kind as it contains a pin that is not relevant. To solve this problem, you could surgically apply "purge" to the schematic as well:

schematic.purge

or even

schematic.simplify

Matthias