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Hi,
I'm trying to run LVS on a "top level" assembly (on the iHP PDK).
This cell is really only assembling other subcells, there are no active devices at all.
Those subcells have passed their own LVS and can be considered good, so really all I want to do is check that the metal/via make the connection they should between the subcells. Those connections can be varied ( so multiple pins of multiple cells connected to the same net ).
Those subcells also have multiple "power pins" exposed and it must be checked that all of them are connected properly.
I was however not able to achieve any of that after trying various approaches.
The very first issue is that I couldn't find any way to black box the extraction itself so that it doesn't extract the "insides" of the subcells.
There is a blank_circuit
( and netlist
and schematic
variants of it which I found out are apparently case sensitive ... ) but AFAICT this acts only after extraction. And that's just no good because the extraction step itself doesn't complete (or at least not in any reasonable time, I have a run that's still running after 12 hours at time of writing this ... ).
I tried instead feeding a GDS where I had manually stripped the subcells to only the pins but I couldn't get that to work either.
So is what I want to do possible with KLayout or should I just give up on it ?
And if it is, then what's the approach I should be doing ?
Cheers,
Sylvain
Comments
Hi @tnt,
This is basically possible, but you need to configure it properly. I think the "substitute cell by a simple version" is the most promising approach.
Again, some test case is required. You can supply it through my private mail if you don't want to share it.
Matthias
Sure attached is an example. It should have all the relevant CDL and includes the "simplified" GDS.
I also included the default PDK LVS script.
Oh, wait a second, I put the wrong GDS in there
(I tried a bunch of variation for my "blackboxing" script and it was not in a good state when I generated it last night ...)
I'll upload a new one during the day.
Here's a good one.
Note that for power pins which have several shaped, there is only a single label ! (That GDS is produced by KLayout from a DEF and that's just what it does ...). So hopefully it can read its own GDS and the user property to figure they belong to the same pin ...
Latest attempt ... There is some progress but I had to so so much hacking in the GDS and in the lvs script that my confidence in the result is going down ...
I'm actually pretty sure it's not checking what I want because I had to use "implicit_connection" for the multiple tt_* modules power pin which does the opposite of what I want : I want it to check that all of the pins are connected through the top level rather than assume they are inside the macro itself.
Note that I don't expect the netlist to match, the IO power rings and inners rings are not connected so those two nets should show an error, but the rest should be fine.
Let me relate what I think I understand about how
Brand X does (or used to do) it.
Just as a schematic may have a symbol or "stop on"
an alt view (like veriloga or spectre), for verification
I see "auLVS" reps on occasion. Believe these somehow
get rid of underlying instances but keep boundary
connectivity and net-layer blockages for a simplest
connection / collision verification. I think the auLVS
rep acts to stop layout hierarchy traversal and replace
with "just the facts (that extraction should care about)"
if invoked (likely default to switch-view membership).
So perhaps you want something like making your own
alt layouts with external nets / pins preserved, and all
internal-only nets all shorted to sub! (or some other
"mostly harmless" flag-node) so as to catch any "wall
breaches"? That ought to be relatively simple, if big-
layout tedious, and checkable.
Hi @dick_freebird,
thanks for the explanation. You're right, something like this was more intuitive. Maybe it is possible to use specific labels to mark a layout cell as "abstract". Unfortunately there are no views in GDS one could use for this purpose.
And @tnt Sorry, I missed the latest update. I will check the files.
Matthias
I took a look at the last sample. I had some trouble figuring out what was hacked in LVS, so I started from scratch with the LVS from IHP: https://github.com/IHP-GmbH/IHP-Open-PDK.
I'm not finished yet, but there are a number of issues I see already.
I can patch LVS with a number of "blank_circuit", "connect_implicit" calls, but there is no external way to do that without LVS patching. The idea is to use some wrapper file that makes these definitions and then includes the original LVS, but that is not compatible with the Python-driver approach. For now, I leave it with patching.
You layout is kind of stripped of all the FEOL parts, so there is an issue with the pwell that IHP introduces: as the pwell is everywhere, it forms a net inside every cell and without a tap it becomes a separate pin. Without "blank_circuit", this pin would be removed as it does not connect to anything. With "blank_circuit" it is not, as that is basically part of the abstract ...
Unfortunately, there are no labels for them, so this net does not have a name and cannot "must connect" (connect explicit) to the ground net. I introduced a label layer on 235/4, so it is possible to give pwell a label. I added this label to all the abstract cells and named it according to the gound net it is supposed to connect to.
I also found a small issue with "blank_circuit": it should be case insensitive as the compare is too, but right now, you need to specify both uppercase schematic and mixed-case layout name. Even though the schematic circuit is already empty, it needs to be included in "blank_circuit" as this marks the circuit as "abstract" and prevents is from being removed as empty.
Another issue are the "K_ONE" and "K_ZERO" pins of "tt_ctrl" for which there is no connection upwards in the hierarchy. Hence, no pins are formed. Such dead pins cannot be matched. A solution is to put a label or a small metal5 patch over these pins in the hierarchy above. But the same is true for many other pins (e.g. um_ena[0] for tt_mux), so I somewhat assume the sample is not completely routed (?)
That needs a little more elaboration ...
I just wonder why this simply example originally took so long, so you started looking for abstracts. This is usually due to ambiguities when parallel busses are involved. This can be mitigated by using net names for matching hints.
Matthias
The GDS included in the example you have is the "simplified one" where all sub cells have been replaced by blank ones with just the pins.
I had noticed the issue with the substrate and I had hacked the LVS to just remove all the "extract devices" and basically anything that wasn't pure metal extraction (since the top level assembly of abstract module is pure metal + via).
But pins exposed but not connected is not an error. The macros are pre-generated and "generic". Then assembled together using only metal. Some times, some functions are not needed and some output pins will be left unconnected ...
In the mean time I found another way to check connectivity so I'm using that for this tapeout so I could move forward.
When I have a more fully complete example of chip that should pass LVS, I'll post it here.
Hi @tnt,
I have attached a version that passes LVS. It is based on the current version of the IHP PD with a few hacks and adding a section with the blank_circuit calls.
grep for "PATCHED_FOR_DISCUSION_2602" to find the changes. Use "run.sh" to run the example.
Layout-wise I added M5 patches to form the pins. I agree that disconnected pins should not be and issue. I think it is specific to the blanked circuits. Normally such pins would be ignored, but not for blanked circuits as pins a taken seriously in that case. Something to consider as an enhancement.
I also added labels to make the substrate connect to VGND or vss. The IHP LVS uses a polygon layer for substrate which is always present and forms pins. The orginal idea was to use global nets which are only created when needed. Hence, this workaround is required for macros not featuring substrate taps.
I created a connection at the lower left to complete the VDD net and connect ring and P&R area. VSS is connected through the substrate already. This means, the missing connection is not detected, except that the "connect_implicits" are not fulfilled. Hence the LVS log contains a corresponding warning. LVS can detect substrate-only connections by using "weak_connect", but IHP LVS does not do that yet.
I'd be interested to see the full case and if there is a performance issue as you say. Please keep me updated.
Thanks,
Matthias
Update: it's actually not that bad ... you don't need to metal5 patches to form real pins. KLayout will ignore schematic pins that are not connected from outside. I have attached a version that does not need these patches.
What is left is the substrate label and the VDD connection that makes the device match.
Matthias