Rename devices with labels in Device Extraction

edited November 1 in Verification

Is there a way to rename devices during device extraction with a given set of labels?
Example Spice output:

* Created by KLayout

.SUBCKT TOP
D$1 1 1 diode_dev A=152519.75592P P=1563.728U
D$2 2 2 diode_dev A=155127.109292P P=1576.494U
D$3 3 3 diode_dev A=151327.92696P P=1557.344U
.ENDS TOP

To this output:

* Created by KLayout

.SUBCKT TOP
DDev_A 1 1 diode_dev A=152519.75592P P=1563.728U
DDev_B 2 2 diode_dev A=155127.109292P P=1576.494U
DDev_C 3 3 diode_dev A=151327.92696P P=1557.344U
.ENDS TOP

Where Dev_A, Dev_B, Dev_C are labels on each respective diode.

I initially thought of creating a custom device extractor that takes in an extra terminal for labels, but from what I've seen no text data gets passed.
Here is an example of the extractor: (Example copied from here: https://www.klayout.de/forum/discussion/2178/problems-encountered-when-changing-the-terminal-declaration-in-the-device-class)

class DiodeExtractor < RBA::GenericDeviceExtractor

  def initialize(name)
    self.name = name
  end

  def setup
    define_layer("P", "Anode")
    define_layer("N", "Cathode ")
    register_device_class(RBA::DeviceClassDiode::new)
  end

  def get_connectivity(layout, layers)
    conn = RBA::Connectivity::new
    conn.connect(layers[0], layers[1])   # collect touching contacts
    conn.connect(layers[1], layers[1])   # combine resistor shapes into one area
    conn
  end

  def extract_devices(layer_geometry)    #layer_geometry are Region Datatypes, no text?
    anode = layer_geometry[0]
    cathode  = layer_geometry[1]
    diode_regions= (anode & cathode).merged
    a = diode_regions.area*dbu*dbu
    p = diode_regions.perimeter*dbu
    device = create_device
    #device.name = "Fred_The_Lonely_Diode"    #If text can be passed then this is where the device would be renamed.
    device.set_parameter(RBA::DeviceClassDiode::PARAM_A, a)
    device.set_parameter(RBA::DeviceClassDiode::PARAM_P, p) 
    define_terminal(device, RBA::DeviceClassDiode::TERMINAL_A, 0, anode[0]);
    define_terminal(device, RBA::DeviceClassDiode::TERMINAL_C, 1, cathode[0]);
  end

end

Comments

  • Hi @blueman_44,

    Right now, the geometry is polygon-only and I do not plan to change that. What you see in the device extractor is a significantly modified version of the original geometry - for example, it is used as a cache key, so it gets normalized. Caching for example would be quite useless when you include device labels too.

    Maybe it is possible to specify some extra input that takes labels only. But as I said, I don't have a plan to implement such a feature. I have not seen layouts with device labels so far.

    What is the specific benefit you see for this feature?

    Matthias

  • The main benefit I would get is having the association between the device type (diode_dev), device name (Dev_A), its coordinates, and its net in one extraction for parsing out. But it would be a 'nice to have' feature, unless there is a more useful application with LVS.

    Thanks!
    Matthew

  • I see similarities here, to what Brand X does - sorta.

    Brand X does not verify directly against layout. There
    is an "extract" process which creates a new cellview
    ("extracted") and creates a flat (at least, in the versions
    of verification I used to know) layout from the hierarchical,
    metal/drawing layers are replaced with metal/net (purpose)
    layers and the net polygons all have net# properties
    assigned; similarly the instances discovered, are
    "replaced" with itty bitty symbol critters and all terminals
    carry an assigned net based on discovery.

    I believe there must be a map-file maintained somewhere.

    There may be a secondary "refine" step which also
    does parasitic scraping and adds more itty bitty
    pcapacitor symbols (what goes on for RLC, no clue).

    So my point here is, I believe that a layout (perhaps
    making use of GDS "properties" as part of PCell
    evaluation / instance creation) "could" be made to
    produce a connectivity-equal, layers-simplified,
    connectivity-bearing GDSII where those "unused"
    properties are "bubbled up" to top level usefulness
    of the sorts described.

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