Running LVS on an inverter in IHP

diarmuid

Hello, I am having difficulty running LVS on an inverter in IHP process.

I have created an inverter.spice and inverter.gds and run the following command in the correct location of the $PDK_ROOT:

python3 run_lvs.py --layout=/home/slice/xschem/tb_inverter/LVS/inverter.gds --netlist=/home/slice/xschem/tb_inverter/LVS/inverter.spice --run_dir=/home/slice/xschem/tb_inverter/LVS --topcell=inverter --top_lvl_pins

Run however errors out complaining it has not found a cell name "inverter" for the layout.

Attached shows the error message and the contents of the extracted.cir.

Only new to this tool so quite confused about this error.
Any help most appreciated!

Thanks,

Diarmuid

dick_freebird

Looks to me like the topCell name is "TOP".

What happens if you edit it to be "inverter" in
the extracted netlist, or assert "--topcell=TOP"?

Perhaps the layout netlister allows you to
assert the topCell name, to get it in the
subcircuit declaration?

diarmuid

Thanks dick_freebird. Some progress there. When I assert "--topcell=TOP", it complained it couldnt find the schematic so I created a TOP.spice (attached) and ran the below.

python3 run_lvs.py --layout=/home/slice/xschem/tb_inverter/LVS/TOP.gds --netlist=/home/slice/xschem/tb_inverter/LVS/TOP.spice --run_dir=/home/slice/xschem/tb_inverter/LVS --topcell=TOP --top_lvl_pins

It appears to have run through giving me an "ERROR : Netlists don't match" at the end, see attached. However, it didnt give me any results to debug the error (attached is a screenshot of my run_dir. Note the logfile has only a timestamp and execution time in it).

Therefore, if it didnt give me any results Im not really sure it did run correctly and perhaps just errored out at some initial step.

Cheers,

Diarmuid

Matthias

Hi @diarmuid,

looks like your layout does not have an substrate and nwell tie. The body terminals of the NMOS and PMOS devices are not connected.

But without the layout files I can't say.

Matthias

diarmuid

Hi @Matthias,

Thanks for the reply. Yes I had to fix a few basic errors and have it LVS clean now. To get the tool to run error free I needed to do the following:

1. I needed to rename my inverter.gds and inverter.spice files to TOP.gds and TOP.spice. Otherwise the tool complained it could not find a cell "TOP". Why exactly does it look for "TOP" and not be ok with my original names?

2. As per above, I save my schematic as a .spice file. Again, to get the tool to work I first needed to run the LVS command to created a "TOP_extracted.cir" file. Then when I ran the tool again, but this time comparing TOP.gds with TOP_extracted.cir, it was LVS clean. Is this the norm - I must run LVS command twice? Does it only compare .gds wtih .cir?

3. When the LVS tool was not clean it only reported "Netlists dont match". How exactly can I debug further? I noticed a file "TOP.lvsdb" appear. Is this some sort of database that can show me where the error is? If so, how do I use it as just looking at the text file I didnt gain any insight.

Thanks,

Diarmuid

diarmuid

actually, please ignore question #1, this was due to a bug on my side!

diarmuid

actually please ignorie #2 and #3. Im ramping up on this tool so prone to asking "silly" questions like these! For anyone following this thread who is a newbie at this tool, my issues was not connecting the bulks correctly. This was evident at the end of the lvsdb file. When fixed, an LVS comparison of .spice and .gds files gave correct results.

It says "INFO: Congratulations! Netlists match". Pity it doesnt show a smiley face like Im used to!