First; thank you; klayout is awesome. I have a question about the "Trace Net" functionality - I'm sorry if it's addressed elsewhere. I understand that the "Trace Net" feature is meant just for visualization, but I would like to use it to extract the labels which are on connected pads in a design with >100 nets, because I haven't been able to find an affordable tool capable of extracting a netlist from a layout. I am able to do this through the "Trace Net" feature by clicking all the nets by hand, exporting the text produced by the net tracer, and then parsing this, but that means I have to click on each net by hand to build the netlist.
Is there any way to automate the selection of pads to be traced, or to run the feature on a group of selected features? If it helps, I know the exact locations of pads on every net I want to trace. I was hoping to be able to script this, but saw in a post in 2014 in this forum that you said the net tracer is not yet accessible through scripts. No problem if there's not a straightforward way to do this. Thanks,
first of all, thanks.
Regarding the net tracer - it's actually designed for tracing single (small) nets, so it won't be able to replace a true netlist extraction tool. I bet you'll quickly reach the limits of that feature, even if there is a way to automate the extraction (which there isn't right now).
Here are some things that are lacking:
Pad labels should be transferred automatically into net names. If that does not work, try to include the label layer into the connectivity list.
Given the limitations I wonder whether automation capabilities really make sense. So I'm afraid, right now there is now (not even elaborate) way to automate the task.
I also have an interest in this.
Since we are using Paths for both electrical connections, and for optical waveguides (using Convert to PCell | Basic.ROUND_PATH functionality), I wonder if something could be done by simply reading data from all the paths in the layout? Presumably, we could scan the layout, and export all the paths (start and end points), plus all the objects (either fixed layout or PCells) with all their pins. We could use text labels on the pins to help identify the pins.
I guess you are looking for a feature to annotate layout with net names, right?
This feature is not the strength of KLayout currently - the net tracer function was mainly intended as an editing aid, less an extraction feature. There is no Ruby binding for the related features yet, so embedding this into a script is not possible currently. But providing the necessary Ruby/Python bindings is still on my TODO list.
In general, I see big demand for more netlist extraction functionality, specifically extraction of big nets and of full netlists (not just single nets). In general, that is feasible, but right now I'm a bit reluctant to follow this path. It's a bit like opening Pandora's box - starting this gives way to a whole universe of new requirements - performance and feature wise.
I implemented a netlist extraction, and posted the code on GitHub - https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK
It searches for paths and ROUND_PATHs, finds out what they are connected to, and generates a Spice netlist file.
Then I can use this file for circuit simulations.
It wasn't too difficult. I've only tested this on a handful of nets so I don't know how well it scales to thousands of connections...
Wow ... I'm impressed!
This is an entirely new field to me. Although I feel that the extraction basically is similar to extracting resistor values from wires.
I saw code for verification of the layouts. Will the DRC feature be applicable in that case too?
DRC – indeed, that's the standard way of doing things. We typically use Calibre DRC, with rules provided by the photonics foundries -- similar to CMOS electronics foundries. However, there are numerous challenges with photonic-DRC.
There is a good article by my colleagues at Gent, Belgium, that discusses some challenges in silicon photonics, including layout, DRC, LVS, etc:
Design Challenges in Silicon Photonics
For example, we have curves. One challenge has been to detect tiny offsets in waveguides. And acute angles. So the approach we are taking is to split some of the verification to go into the regular polygon-based DRC, and put some in the LVS-type verification. What I'm been successfully implementing in KLayout is the latter.
We'll add the physical DRC rules as well later.
p.s. Let me know if you'd like to audit the edX course I have on this topic, if you want to see a bit more behind the scenes about this field. The course includes fabrication and automated testing of participant designs.
Resistor value extraction -- is that something available in KLayout? and nets, etc?
No, not yet ... but I'm getting excited always when I smell reusable functionality ... :-)
Is there any plan to develop a schematic editor in the Klayout format? I'm looking for a way to create symbols that represent photonics functional units, and then connecting them with drawn lines that represent Wave Guide paths.
My goal is to eventually extract a schematic netlist and a layout netlist that can be compared.
There is a vision, but a vision is a plan that maybe dosn't get realized :-)
I'm simply not enough people. A clone procedure would be helpful.
Fun aside, I'm seeing some schematic editors around. Maybe there is a chance to plug one of them together with KLayout.
I'm not really familiar with photonics netlists. I guess that waveguides map to transmission lines in electronic circuits. So the netlist would contain transmission line "devices" which aren't very common elements in schematics. In the electronic world I a transmission line would be represented by two wires rather than one waveguide. So there is a conceptual problem mapping these worlds.
Do you have a sample (layout/netlist) by chance?