Howdy, Stranger!
It looks like you're new here. If you want to get involved, click one of these buttons!
Quick Links
how to start from a spice netlist
hello
i would like to know the way to get from schematic to a layout. if i understand it correct, then its possible to draw a schematic in Xschem and export a spice-netlist. then import this in klayout, then place and route the parts manual, or place the parts export the GDS and let it route from some router. and then export a new spice-netlist including the routing impedances,
is this correct?
and if yes
how do i the spice import?
how can i see what GDS elemet is connected to which net?
Comments
Currently there is no net annotation. You cannot import a netlist. As of now, KLayout is a purely graphical layout editor, not a layout system. I'm sorry.
Matthias
if there are no nets, how can the LVS work? at least some ports need nets as starting point, or not?
LVS works after the fact on its own database derived by logic
from the polygon layout.
GDSII doesn't know from named nets.
What you are asking for is analog layout synthesis and that is
something that's always "coming soon" (for $$$$$$). There is a
large variety of "care-abouts" which go beyond device name and
connectivity, which a SPICE netlist will not express (or even if
represented in analysis, the SPICE analysis per layout iteration
will kill you, relative to how fast a digital STA can be run to
criticize and recenter a P&R iteration).
You might just have to get good at it instead.
thanks for Your answer. unfortunately im nor sure if i understand correctly:
You say, that the LVS software does analyze the layout and is able to find the parts and there dimensions (FETs, resistors, and so on)? and the wiring?
this sounds really complex, i was thinking, the LVS only takes the GDSII-cells and finds there connections.
im absolutely not interested in layout synthesis, im only interested in importing parts form a schematic into KLayout, place the parts, and route it from hand. for the digital standard-cells, i would like the use QRouter if possible.
is this possible?
@olisnr LVS is a physical verification tool. It takes polygons from GDS, regenerates the devices and their connections and compares that with the netlist. It will report success if both the layout-derived netlist and the schematic match.
What you are looking for is not available. You can only draw layouts and use LVS to make sure you have wired correctly. But your problem starts with the word "parts", because for doing so you need a library of "parts" and that (as a part of a PDK) needs to come from someone. Typically these are device PCells or standard cells. That is foundry specific IP and not included in KLayout. Having these parts means you can place them (drag and drop) and wire them (draw paths, place vias). That is a paint job and KLayout won't support you by linking polygons or pins to nets in a schematic. Only LVS is there to tell you that you're correct. But again, LVS needs a setup and that is also foundry IP, packaged inside a PDK and not part of KLayout.
Matthias
thanks. how is it with DEF/LEF import? in principled the LEF should include the GDS and a port/pin-definition (or is this wrong?) and the DEF should include the netlist.
because there is an DEF/LEF import: is it possible to hilight the pins/port-names from LEF-parts?
In digital synthesis you really have two goals - functional
hookup, and timing closure. The P&R tool will grind until
it "makes it so" (or fails). The available values for components
are limited and can only be chosen-between.
Analog design imposes a lot more care-abouts and they all
have to be met, and determining whether they are or aren't
takes substantially more time in the analysis-run, and in
setting up the totality of those.as very-iteration feedback.
I imagine that if you tried, you could make a synthesis
library for "analog stuff" and pretend that only the raw
correct hookup matters. That will get you past wiring, but
are you prepared to develop "timing models" for analog
"stuff" when really the circuit cares about ohmic interconnect
and matching, etc.?
In my experience the routing is the least of it. Getting to what
should be routed without screwing up, that's the time sink.
no, its only im used working with PCB layout-software. and if i draw a schematic, then im really happy to have the possibility to see, what pins in a layout are connected. i think its strange to do chip-layout with out any support from the software.
for an OPAMP can have 30 MOSFETs. and to placing them, one can use the schematic and some ideas about symmetry, thermal-gradients and so on. but the wiring in the end is something that will easy goes wrong, without any support of the software.
it would be enough to highlight all connections of a net. without this, it feels like the times, where we used pre-patterend sticky tape and crepe tape...
its clear, that DEF/LEF is used for digital design and auto-router, but if it can bring the netlist into KLayout, then i would like to use it for analog circuits routed manual.
I do analog ICs (if I'm asked to do digital, it gets done
transistor level and SPICE verification). I never use a
SPICE deck to drive layout, schematic speaks to me
and I lay out from that view. A custom SPICE model
set for LVS (dropping all parasitics that are in the
subcircuits of the mainstream model-pile) is used for
LVS from the schematic side.
If you find that SPICE representation works for you,
then you can go that way. I just find that when the
schematic is clean and expresses analog intent, then
layout follows pretty naturally. SPICE netlists have no
such ordering or annotation of interests such as matching
or routing, unless you were somehow to drive that into
the netlist by schematic artifacts.
Since I make the schematics and do the layout, I have
no worries about communicating intent or making it so.