Capacitance and Resistor LVS checks ignoring R and C values

Comments

• Matthias

  May 2022

  Hi Amro,

  I think you refer to this post, which was basically about the same question: https://www.klayout.de/forum/discussion/comment/7990#Comment_7990

  Maybe you can give me some more details - what was the message you got and how did you model the devices?

  Matthias
• Mohanad_Mohamed

  June 2022

  Hi @Matthias ,

  Thanks for your reply.

  Here is an example on the device that we need to get extracted. the netlist itself doesn't contain c parameter for the capacitor device.

  ************************************************************************
  * Example on missing parameter in Netlist
  ************************************************************************
  
  .SUBCKT TOP 1 2
  
  Cap 1 2 cap_device m=1 l=1u w=1u
  
  .ENDS
  

  and here is the error message:

  

  for more details, we included example layout, LVS deck, and example netlist for testing:

  https://drive.google.com/drive/folders/1Vjc34iVOjcOlc143b6XxbIaCYeXfEFkd?usp=sharing

  Thanks in advance.

  Mohanad
• Matthias

  June 2022

  I see and thanks for the test case.

  The problem is not upon checking, it's upon reading the Spice file. Unfortunately there is not the "one" Spice specification. There are multiple flavours and in this specific case, there is an ambiguity between model name, value specification and a potential third bulk pin.

  KLayout recognizes these forms of cap specs:

  Cx n1 n2 model_name C=value ...
  Cx n1 n2 n3 model_name C=value ...
  Cx n1 n2 value model_name ...
  Cx n1 n2 n3 value model_name ...
  

  Your case matches the first one, except that the value is missing. You can fix this in your case by customizing the Spice reader:

  # A custom Spice file reader delegate that adds a default value
  class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
    def parse_element(s, element)
      if element == "C"
        super(s + " C=0", element)
      else
        super
      end
    end
  end
  
  # Use our specific delegate for reading the Spice file
  reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
  schematic("x.cir", reader)
  

  This will give you caps with a value of 0. You can then apply "ignore_parameter" to skip the capacitance value check.

  Matthias