Reduce split gate option in LVS

Hi Matthias,
In LVS using some complex Flip Flop cells, I encountered the case that Klayout required MOS device reduction option for the extracted net list as shown below. (Sorry "Attach image" file failed to upload at present.)
Extracted circuit
M1Up netA IN1 TOP VSS NMOS L=1U W=1U
M1Low netA IN2 VSS VSS NMOS L=1U W=1U
M2Upr netB IN1 TOP VSS NMOS L=1U W=1U
M2Low netB IN2 VSS VSS NMOS L=1U W=1U

*please note netA and netB is not the same net.

After reduction
M1 netC IN1 TOP VSS NMOS L=1U W=2U
M2 netC IN2 VSS VSS NMOS L=1U W=2U

This reduction option is called "LVS REDUCE SPLIT GATE" in Mentor Caliber for example.
Can this option be implemented for Klayout circuit reduction in future?

Best regarts,
haru_f

Comments

  • edited January 21

    Hi haru_f,

    Ok, here's the image:

    It's easy to implement if there are four transistors involved (that's just a big "if" then). But basically the chain can be more than two pairs and each transistor can be split into more than gates. Will this be important?

    The smartness required in the general case is to conclude that the NetA and NetB nodes are equivalent (== carry the same potential) for symmetry reasons. Hence they can be connected virtually.

    There is a famous example where detecting symmetry is also important for reducing devices:

    I don't know if such a smartness can be implemented.

    Thanks,

    Matthias

  • Hi, Matthias,
    Certainly, theoretically possible to extend the number of vertical and horizontal stages. However, this configuration seems to be very limited application for reducing the area of Flip-Flop cell.
    The number of vertical stages has a limitation on electrical characteristics, and the number of horizontal stages has an area limitation for gate connection.
    Therefore, I think it is sufficient to limit the application to 2 stages for vertical and horizontal.

    Thanks,
    haru_f

  • Hi, Matthias,
    I found this type of "split gate configuration" existed in large size NAND/NOR gate standard cells.
    Thus, could you support up to 4 vertical stacks?
    Thank you very much in your efforts in advance. :(

    Thanks,
    haru_f

  • Well ... this won't be a simple "if" then ...

    Let me check what's possible. I have not started with this issue yet as I'm a bit short of time right now.

    Regards,

    Matthias

  • Hi, Matthias,
    It's okay.
    Until it can be ehhanced, I use extracted netlist as a temporary schematic netlist for those cells.
    Thank you for your effort in advance.
    Thanks,
    haru_f

  • I'm thinking about this ... but it's going to be slightly tricky. But I love taking challenges :)

    Matthias

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