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In LVS using some complex Flip Flop cells, I encountered the case that Klayout required MOS device reduction option for the extracted net list as shown below. (Sorry "Attach image" file failed to upload at present.)
M1Up netA IN1 TOP VSS NMOS L=1U W=1U
M1Low netA IN2 VSS VSS NMOS L=1U W=1U
M2Upr netB IN1 TOP VSS NMOS L=1U W=1U
M2Low netB IN2 VSS VSS NMOS L=1U W=1U
*please note netA and netB is not the same net.
M1 netC IN1 TOP VSS NMOS L=1U W=2U
M2 netC IN2 VSS VSS NMOS L=1U W=2U
This reduction option is called "LVS REDUCE SPLIT GATE" in Mentor Caliber for example.
Can this option be implemented for Klayout circuit reduction in future?