LVS for compound semiconductors

Hello, I am pulling together a design PDK for a GaAs HEMT process, The DRC is straight forward but the LVS looks quite involved and sample code and the API classes are targeting silicon devices. It looks like i would need to build a GenericDeviceExtractor for the custom HEMT device. Does anyone have samples code they could share and/or share any experience in doing this?

Comments

  • A JFET extractor would be ideal but a MOS extractor could
    probably be convinced to work you might need to make a
    bogus "active_area" polygon to satisfy the logic?).

    Me, I really prefer text-tagged features (like "D" would be:

    ((N+ in active containing the origin of a text with value
    "HEMT") containing the origin of a text with value "D")

    ) rather than trying to recognize based only on printable-
    layer features.

    There is some facility for making recognition-texts work,
    but I don't claim to understand the details / limits / style.

  • Hi,

    maybe you can give a sample for a HEMT layout? A sketch will do.

    The texted approach is always available, but still you need to identify the ports - the polygons to which the wires will connect.

    Matthias

  • Hi Matthias,
    attached is the GDS txt file of a single 3 terminal device. Let me know if you need further explanation of layers. A sample of a texted approach with "S", "D", "G" might be a good start for me to understand how to use txt origins to recognize a device with its associated size.
    Regards,
    Dave O.

  • Hi dosika,

    the sample looks quite similar to a usual three-terminal MOS device.

    So 3/0 is the "diffusion area" and 7, 11 or 9 is the "poly" area. I'd start with this analogy.

    I understand the true device recognition is somewhat more complex. Eventually you'd probably need some boolean operations to filter out the area which is truly "gate". In a normal MOS device this is "diffusion AND poly". But you can use combinations of layers to filter out irrelevant combinations.

    Matthias

  • Hi Mathias,

    the process is a subtractive on and based on a epitaxial layer stack. I attached a cleaner GDS with layer desc below.

    • layer 3/0 is an isolation implant so the area outside the device sees a He+ implant damaging all the conductive layers.
    • layer 5/0 is a ohmic contact metalization layer for source and drain
    • layer 9/0 and 11/0 are the gate metalization (two stacked connected layers forming a T structure)
    • layer 14/0 is a via layer to allow M1 layer 18/0 to connect to the lower metals
    • layer 7/0 is a recess etch to access a buried layer (the channel) in the active device

    Regards,
    Dave O.

  • edited July 13

    Hi Dave,

    I see your point.

    First problem is that KLayout currently only has MOS device, no FET. If you can live with the implications, you can try to go ahead.

    The problem is basically to map your problem to the (symmetric) MOSFET device template, which is made up from three regions: the drain, the gate and the source. For the picture see here: https://www.klayout.de/doc-qt5/manual/lvs_device_extractors.html#h2-146

    The trick is now that source/drain and gate do no really need to be n+ or p+ doped silicon or polysilicon as in CMOS transistors, but can be any kind of polygons.

    I'd suggest to try using "9/0 over 7/0" for the "gate area" and "7/0" similar to a CMOS active area. As you seem to have a SOI like process, you may not need a 4-terminal device. So we can skip bulk/well. Source drain will be defined by "7/0 minus 9/0".

    Although "7/0 minus 9/0" isn't a conductive layer, it still needs to act as a receiver for the terminals ("tS", "tD"), so we need to include it in the connectivity stack (KLayout will put special polygons there which are connected to the device terminals. In order to attach to the device, these polygons need to become part of the connectivity):

    recess = input(7, 0)
    gate = input(9, 0)  # bottom I assume
    gate_top = input(11, 0)
    sd_contact = input(5, 0)
    sd = recess - gate
    
    extract_devices(mos3("HEMT"), { "SD" => sd, "G" => (gate & recess),  "tS" => sd, "tD" => sd, "tG" => gate })
    
    connect(gate, gate_top)
    connect(sd, sd_contact)   # provided layer 5/0 touches or overlaps layer 7/0!
    ... further connections ...
    

    Matthias

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