LVS for compound semiconductors

Hello, I am pulling together a design PDK for a GaAs HEMT process, The DRC is straight forward but the LVS looks quite involved and sample code and the API classes are targeting silicon devices. It looks like i would need to build a GenericDeviceExtractor for the custom HEMT device. Does anyone have samples code they could share and/or share any experience in doing this?


  • A JFET extractor would be ideal but a MOS extractor could
    probably be convinced to work you might need to make a
    bogus "active_area" polygon to satisfy the logic?).

    Me, I really prefer text-tagged features (like "D" would be:

    ((N+ in active containing the origin of a text with value
    "HEMT") containing the origin of a text with value "D")

    ) rather than trying to recognize based only on printable-
    layer features.

    There is some facility for making recognition-texts work,
    but I don't claim to understand the details / limits / style.

  • Hi,

    maybe you can give a sample for a HEMT layout? A sketch will do.

    The texted approach is always available, but still you need to identify the ports - the polygons to which the wires will connect.


Sign In or Register to comment.