dai

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• Thank you, @Matthias I think I should do a macro for this. dai

  in GDS to DEF Comment by dai August 23
• Hi @Matthias You are right. My lambda is not match with coordinates in GDS layout file(see attached picture). I changed my lambda so it saved now. If you can show me how to map layer in gds with layer in tech file of magic tool? (Image) Thank you…

  in GDS to DEF Comment by dai August 12
• Hi Matthias, I am working on extracting GDS to an RC file, and I initially tried using OpenRoad (openRCX) for this purpose. However, since this tool requires a DEF file as input, I researched further and found that the Magic tool might be more suit…

  in GDS to DEF Comment by dai August 9
• I understand. Thank you, @Matthias dai

  in GDS to DEF Comment by dai August 2
• Thank you for your suggestion , @Matthias. I will follow that way. dai

  in XNOR or NXOR option in klayout Comment by dai May 22
• Never mind, @Matthias. I found the way : A xor B = C and then ( A + B ) xor C = D. D will be contains what is same between A and B Thank you, dai

  in XNOR or NXOR option in klayout Comment by dai May 21
• Hi @Matthias , I used strmxor.exe to compare to input GDS(command: strmxor.exe input1.gds input2.gds output.gds), I got output GDS that contains what is different between them. If do we have any way to write to output what is same between them? Tha…

  in XNOR or NXOR option in klayout Comment by dai May 21
• Hi @Matthias, I tried with specify certain name and the result is same. With "all cells" I did not get the message more. I sent you the test case by email, please check your email. Thank you, dai

  in Get exception error when delete instance Comment by dai April 1
• Thank you, @Matthias dai

  in How can do a py macro and run in batch mode(without GUI) Comment by dai June 2023
• i saw it in forum. :) thank @StefanThiede dai

  in Can KLayout do Layout comparison （LVL）？ Comment by dai February 2023
• Thank you, @StefanThiede can you show more detail?. Where do i find this tool on klayout? (Image) dai

  in Can KLayout do Layout comparison （LVL）？ Comment by dai February 2023
• Hi @Matthias , like above we can do on GUI. can we do compare layout vs layout like above by macro?. Please let me know If you have any code example. Thank you, dai

  in Can KLayout do Layout comparison （LVL）？ Comment by dai February 2023
• Hi @Matthes , It works perfectly Thank you, dai

  in split_gate for netlist object Comment by dai January 2023
• Thank you, @sekigawa dai

  in User properties not saved when save file Comment by dai January 2023
• Hi @Max, Thank you for asking. I have done my macro so it is fine for me now. But if i have ChipR i want to compare speed with it to see if i can improve my macro more. dai

  in The parasitic resistance extraction tool based on Klayout Comment by dai January 2023
• hi @Matthias it is working now. Thank you very much,@Matthias. :) dai

  in Klayout 0.28 was crashed when click on "Netlist Database Browser" Comment by dai December 2022
• Hi @Matthias Yes, it is an invalid layer id. Thank you, dai

  in Klayout get crash when run get_info Comment by dai November 2022
• Hi @Matthias , I found the cause for it. There are some layers merged to one. (Image) Thank you, dai

  in get layer from net trace issue Comment by dai November 2022
• Hi @dick_freebird , I'm not sure i understand all your thing. the technology i doing with just support two type of via( square(32x32), rectangle(32x80)) In this case i just want to flag to @Matthias about the error. I trying extract resistor of spe…

  in Extract resistor issue Comment by dai November 2022
• Thank you, @dick_freebird and @Matthias I think i have to subdivide net into pieces because my net is complex and layout guys just want to show resistance between two specified points that they can select. dai

  in How to specify W,L of resistor Comment by dai November 2022
• Thank you, @Matthias My connector should be on short edge of via if shape of via is rectangle(this relate to value of resistor). If it just square then don't need to care it is horizontal or vertical. connector = via.extents(0,1.dbu) it works also…

  in Extract resistor issue Comment by dai November 2022
• Hi @Matthias BTW Have any function help to calculate resistance from node 5 to node 6 in this picture?. I can not use netlist.simplify Because it combine all resistor to one. I trying to flag where is high resistor compare others. (Image) Thank y…

  in How to specify W,L of resistor Comment by dai November 2022
• Hello @Matthias Yes, it is terminals. i trying extract resistor of polygon shape(L,T.. shape), i split polygons to squares and each square is a resistor so it form resistor like that. Here is a example. (Image) Thank you so much. dai

  in How to specify W,L of resistor Comment by dai November 2022
• Thank you, @Matthias

  in Extent an edge to a box Comment by dai November 2022
• Hi @hycmos Thank you very much. Can you give us the link to download ChipR again? I can not download from the link you sent. dai

  in The parasitic resistance extraction tool based on Klayout Comment by dai October 2022
• Thank you, @Matthias dai

  in Return of DRC is not edge pair Comment by dai June 2022
• Thank you, @Matthias dai

  in separation edges to edges issue Comment by dai June 2022
• Thank you, @Matthias I have extended the edge to tiny polygon(i know it is not good solution but it can resolve my issue) and apply space DRC to them (Quote) Here is the way i created the edges, (Quote) i also attached the layout here. thanks dai

  in separation edges to edges issue Comment by dai June 2022
• Thank @Matthias. Thank @dick_freebird.

  in schematic vs schematic (SVS) not (LVS) Comment by dai May 2022
• Hi @Matthias Do you have any way to ignore or set tolerance for parameter for SVS check?. two my netlists has a different width of device so it flag connection mismatch also. It should be show property mismatch only. Thank you, dai

  in schematic vs schematic (SVS) not (LVS) Comment by dai May 2022
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