laurent_c
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Long time agoa I lost a file with the same error, since then, I always have a backup with that option. Still with an older version you can use the backup option in the setup menu : [File] - [Setup] then Application - General : Number of backup file…
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Do you have some connection by drain/source merge by overlapping 2 cells ? If yes, you may need the cheat command line : cheat("BUF1", "any_other_CELL") { the extract_devices lines of your LVS } You have an example in that LV…
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Have you tried the command to choose the number of threads ? # Use 4 CPU coresthreads(4) Laurent
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I have tried to use this decompose_trapezoids method, but my syntax is no good in my LVS file : POLY = polygons(1,0)ACTIVE = polygons(2,0)Gates = POLY & ACTIVEGates_as_quadrilaters = Gates.decompose_trapezoids There is probably something missi…
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Thank you very much Sekigawa, it is exactly what I was looking for :) I would have never found by myself the syntax of this macro : thank you for your help ! Regards, Laurent
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Thank you Sekigawa for your very complete and very instructive method. However, my goal is to extend the KLAYOUT DRC::DRCLayer class with 3 parameters, because I already used that class for other purpose. Best regards, Laurent
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Thank you Sekigawa, you are right : it is saved to the KLayout directory. I finally solved it this way (as I save the LVS result) : File.open(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_myInfo.txt"), "w…
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Perfect. Thank you Matthias !
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It seems that this script is not working anymore ... lv.each_annotation { |a| rulers << a }
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Here is a macro : https://www.klayout.de/forum/discussion/368/dice-count-gross-die-yield-and-wafermap-on-a-layout This is the same method as my Android app : Wafer gross die yield and cost But with KLayout, you get the wafermap in GDS format as a r…
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Assuming a via width of 100nm, I solved it this way : via.enclosed(metal, projection, 20.nm, two_opposite_sides_allowed, one_side_allowed).with_length(100.nm).output("Metal enclosing via > 20nm on two opposite sides") BRgds, Laurent
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Assuming a via width of 100nm, I solved it this way : via.enclosed(metal, projection, 20.nm, two_opposite_sides_allowed, one_side_allowed).with_length(100.nm).output("Metal enclosing via > 20nm on two opposite sides") BRgds, Laurent
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Oups, my exact command was : via.enclosed(metal, projection, 20.nm, two_opposite_sides_allowed, three_sides_allowed).output("Metal enclosing via > 20nm on two opposite sides") BRgds, Laurent
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I just found out that the following command does not work in some strange cases below : via.enclosed(metal, projection, 20.nm, two_sides_allowed, three_sides_allowed).output("Metal enclosing via > 20nm on two opposite sides") (Image) …
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Synopsys has its explanation here : https://www.synopsys.com/glossary/what-is-parasitic-extraction.html StarRC is based on Look-Up tables : it could be a target for KLayout - but which look-up tables ? QuickCapNX is a 3D field solver for RF
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Actually, there are 2 kinds of parasitic extraction : a precise one for RF, any LNA or antenna needs a precises R and C extraction, maybe in 3-D. But for the digital place&route a less precise extraction but fast R-C extraction will do it. The s…
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"original" for me is the result of place&route of OpenROAD. I am trying to run some check on it, so "original" can be rectangles, polygons or paths from the current level of a hierarchy below. BRgds, Laurent
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Indeed, I was using the deep mode, but with random shapes (polygons, paths, ...). Now, it works fine in tile mode, but not in deep mode :'( As usual, I was using your latest version ;) , now, I use the version of December 2. Laurent
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Thank you Matthias, furthermore I needed to mixed moved and sized functions, it perfectly meets my need, except ... that I cannot resize the result. As in your exemple : sized_bottom_left = original.sized(0.5.um, 0).sized(0, 0.5.um).moved(0.5.um, -…
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Actually, OpenRCX does not extract the parasitic ; it calls the software recommended by the foundry (a commercial tool :s ) as it is explained here : https://github.com/The-OpenROAD-Project/OpenRCX/blob/master/doc/calibration.txt Laurent
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Thank you Matthias, it more efficient than my command. As I like to have the all DRC check in 1 line I have compacted as follows : ;) M1.edges.without_angle(0).without_angle(90).without_angle(45).without_angle(-45).output("M1_angle", &qu…
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By the way, if the klayout lvsdb file that results from a KLayout LVS could be read by XSCHEM to find the correspondence between schematic and layout, it would be great :smiley: Laurent
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Thank you Matthias, yep, it seems to be for the same process ... and it works fine ... my next step is to add the body pin. @dick : the third pins is used to add the parasitic capacitance, and my case, yes, it the bulk :p ! and the LVS is OK :) B…
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I just find that the proper syntax is : extract_devices(resistor_with_bulk("RPolyRes_Bulk", 333), { "R" =>; resistor, "C" =>; poly_not_resistor, "W" >; bulk }) This OK to check a resistor like : R0…
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I just found my solution here : https://www.klayout.de/forum/discussion/comment/6775 Laurent
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Thank you Matthias and Stefan. I found my way to write the file for the OpenROAD flow as I wrote in : https://github.com/The-OpenROAD-Project/OpenROAD/discussions/1919 BRgds, Laurent
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Hi Jim, Here a complete xml file compatible with in-line execution : <?xml version="1.0" encoding="utf-8"?><klayout-macro> <description/> <version/> <category>drc</category> <prolog/> &…
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Hi Matthias, Thank you, then the method for the second case becomes : VM1 = VIA.enclosed(METAL, 0.01, projection, one_side_allowed)VM2 = VIA.enclosed(METAL, 0.01, projection, two_sides_allowed)VM3 = VIA.enclosed(METAL, 0.01, projection, three_side…
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Is there a way to use the waivers options like for the separation check ? For example, for 2 opposite sides : METAL.enclosing(VIA, 0.01, projection, one_side_allowed, two_sides_allowed).output("METAL_enc_VIA", "rule xy : Min. Metal …